Triple-Loop Control Configuration for Grid-Connected LCL-Filtered Inverters Based on Time-Domain Design

Abstract

This paper concern with the design of single resonant controllers in triple-loop control configuration for three phase grid-connected inverters based on time-domain analysis for precise tracking in order to achieve fast transient response and reduce grid-current harmonics. It is well-known that in grid-connected LCL-filtered inverters, current behavior directly sets the exchange of power between the two. The most commonly used current control configurations are single and double loop control schemes. Recently, several methods have been proposed to enhance system efficiency by modeling triple-loop control architecture for grid-connected inverters. In triple-loop control scheme the outer loop regulates the grid side inductor current, the middle loop regulates capacitor voltage, and the inner loop regulates either inverter side inductor current or capacitor current. Different regulators have been suggested in literature for triple-loop structure, where design of resonant controllers for this structure was barely investigated, especially closed-loop time-domain transient performance analysis.This paper presents time-domain based design of proportional-resonant controller in triple-loop configuration for three-phase grid-connected inverter. Since in triple loop-configuration system variables are measured to fed-back to each control loops, when those variables act as disturbances, they can be easily eliminated in the other control loops. In case most of the disturbance measured and appropriately cancelled in corresponding plants, the current \ voltage regulation problem reduced to tracking challenge only. Therefore, it would be beneficial to impose transient response based on desired magnitude behavior. In addition, control strategy for balancing of the DC-link capacitors voltages is shown herein, in addition to the proposed triple loop control configuration. Experimental and simulations results are also presented to validate the proposed design methodology.