Arpan Manna, Subham Saha, Rakesh Das, Chandan Bandyopadhyay, H. Rahaman
{"title":"All optical design of cost efficient multiplier circuit using terahertz optical asymmetric demultiplexer","authors":"Arpan Manna, Subham Saha, Rakesh Das, Chandan Bandyopadhyay, H. Rahaman","doi":"10.1109/ISED.2017.8303945","DOIUrl":null,"url":null,"abstract":"In this work we present an efficient multiplication technique using terahertz optical asymmetric demultiplexer (TOAD) in all optical domain. Two approaches are presented here. The first model is a hierarchical design where we have shown a pipelined implementation of array multiplier for unsigned numbers. The second design is the improved design of the first one as it can work for both signed and unsigned numbers. Initially we have shown an n-bit model and afterwards illustrated it for a 4-bit circuit. In terms of design overhead, the second design is more than 50 percent cost efficient than the first one. Design analysis for both the models is presented in the later part of the work.","PeriodicalId":147019,"journal":{"name":"2017 7th International Symposium on Embedded Computing and System Design (ISED)","volume":"177 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 7th International Symposium on Embedded Computing and System Design (ISED)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISED.2017.8303945","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
In this work we present an efficient multiplication technique using terahertz optical asymmetric demultiplexer (TOAD) in all optical domain. Two approaches are presented here. The first model is a hierarchical design where we have shown a pipelined implementation of array multiplier for unsigned numbers. The second design is the improved design of the first one as it can work for both signed and unsigned numbers. Initially we have shown an n-bit model and afterwards illustrated it for a 4-bit circuit. In terms of design overhead, the second design is more than 50 percent cost efficient than the first one. Design analysis for both the models is presented in the later part of the work.