Pub Date : 2017-12-01DOI: 10.1109/ISED.2017.8303904
S. Chakraborty
Over the years, electronic design automation (EDA) has been moving up the design abstraction ladder. Starting from automating tasks like placement, floor-planning and routing in integrated circuits design, EDA now encompasses many system-level design tasks. However, the next challenge facing the EDA community is to develop methods and also tools for cyber-physical systems (CPS) design. For these systems, physical processes, control algorithms that control these processes, and the computation and communication platforms on which these control algorithms are implemented — are all modeled and designed in a tightly integrated fashion. Currently available EDA methods and tools are not equipped to handle such integrated modeling and design. In particular, there is a big disconnect between modeling tools — like Matlab/Simulink — that are used for modeling plant dynamics and designing their controllers, and the tools that are used to design and configure the hardware/software platforms on which these controllers are eventually implemented. In this extended abstract we discuss the consequences of this disconnect and possible ways of addressing this situation.
{"title":"EDA for cyber-physical systems","authors":"S. Chakraborty","doi":"10.1109/ISED.2017.8303904","DOIUrl":"https://doi.org/10.1109/ISED.2017.8303904","url":null,"abstract":"Over the years, electronic design automation (EDA) has been moving up the design abstraction ladder. Starting from automating tasks like placement, floor-planning and routing in integrated circuits design, EDA now encompasses many system-level design tasks. However, the next challenge facing the EDA community is to develop methods and also tools for cyber-physical systems (CPS) design. For these systems, physical processes, control algorithms that control these processes, and the computation and communication platforms on which these control algorithms are implemented — are all modeled and designed in a tightly integrated fashion. Currently available EDA methods and tools are not equipped to handle such integrated modeling and design. In particular, there is a big disconnect between modeling tools — like Matlab/Simulink — that are used for modeling plant dynamics and designing their controllers, and the tools that are used to design and configure the hardware/software platforms on which these controllers are eventually implemented. In this extended abstract we discuss the consequences of this disconnect and possible ways of addressing this situation.","PeriodicalId":147019,"journal":{"name":"2017 7th International Symposium on Embedded Computing and System Design (ISED)","volume":"164 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121249669","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/ISED.2017.8303921
Mrinal Goswami, A. Narzary, Govind Raj, B. Sen
Bit rotation and shifting are two very important operations in many digital logic applications. A barrel shifter can perform rotation and shifting of multiple bits in one cycle. Alternatively, reversible logic is gaining much attention due to its loss-less information processing and low-power dissipation in the logic synthesis. This paper deals with a reversible bi-directional logarithmic barrel shifter that performs rotation of data bits in both the directions. Results establish that the proposed design outperforms the previous designs in terms of quantum cost, number of garbage outputs, hardware cost and the total number of gates. Moreover, the testability feature of the proposed barrel shifter is analyzed with the integer linear program (ILP) method, which reports 7 test vectors of size 6 as a minimal complete test set for single as well as multiple stuck-at faults.
{"title":"Design of reversible bidirectional logarithmic barrel shifter","authors":"Mrinal Goswami, A. Narzary, Govind Raj, B. Sen","doi":"10.1109/ISED.2017.8303921","DOIUrl":"https://doi.org/10.1109/ISED.2017.8303921","url":null,"abstract":"Bit rotation and shifting are two very important operations in many digital logic applications. A barrel shifter can perform rotation and shifting of multiple bits in one cycle. Alternatively, reversible logic is gaining much attention due to its loss-less information processing and low-power dissipation in the logic synthesis. This paper deals with a reversible bi-directional logarithmic barrel shifter that performs rotation of data bits in both the directions. Results establish that the proposed design outperforms the previous designs in terms of quantum cost, number of garbage outputs, hardware cost and the total number of gates. Moreover, the testability feature of the proposed barrel shifter is analyzed with the integer linear program (ILP) method, which reports 7 test vectors of size 6 as a minimal complete test set for single as well as multiple stuck-at faults.","PeriodicalId":147019,"journal":{"name":"2017 7th International Symposium on Embedded Computing and System Design (ISED)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127174484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/ISED.2017.8303926
D. Dennis, Ayushi Priyam, Sukhpreet Singh Virk, Sajal Agrawal, Tanuj Sharma, Arijit Mondal, K. C. Ray
In this paper, development of a fully synthesizable 32-bit processor based on the open-source RISC-V (RV32I) ISA is presented. This processor is designed for targeting low-cost embedded devices. A RISC-V development and validation framework with assembling tools and automated test suits is also presented in this paper. The resulting processor is a single core, in-order, non-bus based, RISC-V processor with low hardware complexity. The proposed processor is implemented in Verilog HDL and further prototyped on FPGA "Spartan 3E XC3S500E" board. This is found that the maximum operating frequency is 32MHz. The power is estimated to be 7.9mW using Xilinx Power Analyzer.
本文介绍了一种基于开源RISC-V (RV32I) ISA的全合成32位处理器的开发。该处理器是针对低成本嵌入式设备而设计的。本文还介绍了具有装配工具和自动化测试套装的RISC-V开发和验证框架。由此产生的处理器是一个单核、有序、非基于总线的RISC-V处理器，硬件复杂性低。提出的处理器在Verilog HDL中实现，并在FPGA“Spartan 3E XC3S500E”板上进一步原型化。由此发现，最大工作频率为32MHz。使用Xilinx功率分析仪估计功率为7.9mW。
{"title":"Single cycle RISC-V micro architecture processor and its FPGA prototype","authors":"D. Dennis, Ayushi Priyam, Sukhpreet Singh Virk, Sajal Agrawal, Tanuj Sharma, Arijit Mondal, K. C. Ray","doi":"10.1109/ISED.2017.8303926","DOIUrl":"https://doi.org/10.1109/ISED.2017.8303926","url":null,"abstract":"In this paper, development of a fully synthesizable 32-bit processor based on the open-source RISC-V (RV32I) ISA is presented. This processor is designed for targeting low-cost embedded devices. A RISC-V development and validation framework with assembling tools and automated test suits is also presented in this paper. The resulting processor is a single core, in-order, non-bus based, RISC-V processor with low hardware complexity. The proposed processor is implemented in Verilog HDL and further prototyped on FPGA \"Spartan 3E XC3S500E\" board. This is found that the maximum operating frequency is 32MHz. The power is estimated to be 7.9mW using Xilinx Power Analyzer.","PeriodicalId":147019,"journal":{"name":"2017 7th International Symposium on Embedded Computing and System Design (ISED)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126768866","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This article presents a voltage mode filter. This circuit has the following important features: It is designed using CCDDCCTA. All response like LP, HP, BP, AP, & notch are obtained without alteration of the configuration. Response of all filters is electronically tunable and Low sensitivity. Operation of proposed circuit is tested using 25µm CMOS process through PSPICE simulation. Simulated outputs match with the theoretical results.
{"title":"Voltage mode universal filter design using CCDDCCTA","authors":"Rupam Das, Kaustav Mallick, Tunisha Tanvi, Kanishka Sah","doi":"10.1109/ISED.2017.8303942","DOIUrl":"https://doi.org/10.1109/ISED.2017.8303942","url":null,"abstract":"This article presents a voltage mode filter. This circuit has the following important features: It is designed using CCDDCCTA. All response like LP, HP, BP, AP, & notch are obtained without alteration of the configuration. Response of all filters is electronically tunable and Low sensitivity. Operation of proposed circuit is tested using 25µm CMOS process through PSPICE simulation. Simulated outputs match with the theoretical results.","PeriodicalId":147019,"journal":{"name":"2017 7th International Symposium on Embedded Computing and System Design (ISED)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129848289","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/ISED.2017.8303945
Arpan Manna, Subham Saha, Rakesh Das, Chandan Bandyopadhyay, H. Rahaman
In this work we present an efficient multiplication technique using terahertz optical asymmetric demultiplexer (TOAD) in all optical domain. Two approaches are presented here. The first model is a hierarchical design where we have shown a pipelined implementation of array multiplier for unsigned numbers. The second design is the improved design of the first one as it can work for both signed and unsigned numbers. Initially we have shown an n-bit model and afterwards illustrated it for a 4-bit circuit. In terms of design overhead, the second design is more than 50 percent cost efficient than the first one. Design analysis for both the models is presented in the later part of the work.
{"title":"All optical design of cost efficient multiplier circuit using terahertz optical asymmetric demultiplexer","authors":"Arpan Manna, Subham Saha, Rakesh Das, Chandan Bandyopadhyay, H. Rahaman","doi":"10.1109/ISED.2017.8303945","DOIUrl":"https://doi.org/10.1109/ISED.2017.8303945","url":null,"abstract":"In this work we present an efficient multiplication technique using terahertz optical asymmetric demultiplexer (TOAD) in all optical domain. Two approaches are presented here. The first model is a hierarchical design where we have shown a pipelined implementation of array multiplier for unsigned numbers. The second design is the improved design of the first one as it can work for both signed and unsigned numbers. Initially we have shown an n-bit model and afterwards illustrated it for a 4-bit circuit. In terms of design overhead, the second design is more than 50 percent cost efficient than the first one. Design analysis for both the models is presented in the later part of the work.","PeriodicalId":147019,"journal":{"name":"2017 7th International Symposium on Embedded Computing and System Design (ISED)","volume":"177 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114523597","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/ISED.2017.8303923
P. Roy, Amiya Sahoo, H. Rahaman
In recent years a new generation of droplet based lab-on-chip device termed as Digital Microfluidic Biochip(DMFB) has found wide applications in the field of clinical diagnostics, DNA sequencing, drug design and environmental toxicity monitoring applications. Optical detection in DMFB is of major significance as it involves detection accuracy of the final results that determines the decision for clinical diagnostic solutions. In this work we propose the design of an adaptive detection system comprising of automated digital detection analyser coupled with Digital Microfluidic Biochips. The system performs automated analysis of the detection results for an obtained set of samples for the same patient and predicts the actual trend of the detection results. The technique is based on iterative averaging combined with adaptive manipulation of detection ranges determined through precharacterized values. This method provides higher detection accuracy (in the event of uncertainty resulted when no clear detection majority is available) with an approximated prediction of the trend of the extent of infection or abnormality of the targeted parameter. The design is simulated in FPGA platform and the detection results display fair amount of accuracy particularly in line with conventional laboratory methods.
{"title":"Adaptive medical detection system: An iterative averaging method for automated detection analysis using DMFBs","authors":"P. Roy, Amiya Sahoo, H. Rahaman","doi":"10.1109/ISED.2017.8303923","DOIUrl":"https://doi.org/10.1109/ISED.2017.8303923","url":null,"abstract":"In recent years a new generation of droplet based lab-on-chip device termed as Digital Microfluidic Biochip(DMFB) has found wide applications in the field of clinical diagnostics, DNA sequencing, drug design and environmental toxicity monitoring applications. Optical detection in DMFB is of major significance as it involves detection accuracy of the final results that determines the decision for clinical diagnostic solutions. In this work we propose the design of an adaptive detection system comprising of automated digital detection analyser coupled with Digital Microfluidic Biochips. The system performs automated analysis of the detection results for an obtained set of samples for the same patient and predicts the actual trend of the detection results. The technique is based on iterative averaging combined with adaptive manipulation of detection ranges determined through precharacterized values. This method provides higher detection accuracy (in the event of uncertainty resulted when no clear detection majority is available) with an approximated prediction of the trend of the extent of infection or abnormality of the targeted parameter. The design is simulated in FPGA platform and the detection results display fair amount of accuracy particularly in line with conventional laboratory methods.","PeriodicalId":147019,"journal":{"name":"2017 7th International Symposium on Embedded Computing and System Design (ISED)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126285729","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/ISED.2017.8303938
Atul Kumar Dwivedi, S. Bhatt, Subhojit Ghosh
Fractional order representation has been more effective in analyzing various physical systems more efficiently as compared to conventional integer order representation. Fractional order representation allows higher order integer systems to be replaced by small fractional order equivalent systems. In this paper, fractional order filters are designed using Swarm intelligence based evolutionary optimization algorithm. The designed filters have been compared with other state of the art evolutionary optimization techniques. In order to evaluate the order reduction by the proposed technique the designed filters are converted to equivalent higher order digital filter. The applicability of the designed filters for real time applications has been validated using TMS320F2812 DSP processor.
{"title":"Fractional order butterworth filter design using Artificial Bee colony algorithm","authors":"Atul Kumar Dwivedi, S. Bhatt, Subhojit Ghosh","doi":"10.1109/ISED.2017.8303938","DOIUrl":"https://doi.org/10.1109/ISED.2017.8303938","url":null,"abstract":"Fractional order representation has been more effective in analyzing various physical systems more efficiently as compared to conventional integer order representation. Fractional order representation allows higher order integer systems to be replaced by small fractional order equivalent systems. In this paper, fractional order filters are designed using Swarm intelligence based evolutionary optimization algorithm. The designed filters have been compared with other state of the art evolutionary optimization techniques. In order to evaluate the order reduction by the proposed technique the designed filters are converted to equivalent higher order digital filter. The applicability of the designed filters for real time applications has been validated using TMS320F2812 DSP processor.","PeriodicalId":147019,"journal":{"name":"2017 7th International Symposium on Embedded Computing and System Design (ISED)","volume":"1965 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131244378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/ISED.2017.8303913
Moumita Das, A. Banerjee, B. Sardar
The objective of this paper is to examine the common branch predictor designs available in literature, and characterize their accuracy versus storage performance. As expected, many of the predictors which are known to have high accuracy in general, lose out on performance when exercised in low storage scenarios. This paper presents an empirical evaluation of different branch predictors at various storage points and the resulting effect on processor performance in terms of prediction accuracy and latency. We present our findings using the branch predictors and the traces of the Championship Branch Predictor-2 benchmarks. We believe that our study will be extremely beneficial for choosing a branch predictor design for embedded processors working in resource constrained environments.
{"title":"An empirical study on performance of branch predictors with varying storage budgets","authors":"Moumita Das, A. Banerjee, B. Sardar","doi":"10.1109/ISED.2017.8303913","DOIUrl":"https://doi.org/10.1109/ISED.2017.8303913","url":null,"abstract":"The objective of this paper is to examine the common branch predictor designs available in literature, and characterize their accuracy versus storage performance. As expected, many of the predictors which are known to have high accuracy in general, lose out on performance when exercised in low storage scenarios. This paper presents an empirical evaluation of different branch predictors at various storage points and the resulting effect on processor performance in terms of prediction accuracy and latency. We present our findings using the branch predictors and the traces of the Championship Branch Predictor-2 benchmarks. We believe that our study will be extremely beneficial for choosing a branch predictor design for embedded processors working in resource constrained environments.","PeriodicalId":147019,"journal":{"name":"2017 7th International Symposium on Embedded Computing and System Design (ISED)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115541362","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/ISED.2017.8303929
Sharbani Purkayastha, S. Mukherjee
With increasing size and complexity of FPGA, placement has lately become the main concern in FPGA physical design. The existing approaches use both packing and placement technique for FPGA placement separately. Unlike the existing methods, we propose a novel global placement approach for heterogeneous FPGA without undergoing packing. The focus of the work is to find the global placement of heterogeneous FPGA architecture with minimum wire length. The existing FPGA placement algorithms first consider packing the logic elements, LUTs and FFs into BLEs then place it in a target FPGA architecture. The proposed global placement approach avoids packing thereby removes the overhead of packing phase in FPGA design. The proposed method consists of (1) Clustering, (2) Fixed block (I/O) placement, (3) Window selection, (4)Placing hard blocks using lookahead legalization.(5) Placing soft blocks using lookahead legalization. The proposed algorithm is evaluated and tested on ISPD 2016 benchmark circuits. The obtained results are found at par with the results of other existing techniques with respect to total wire length.
{"title":"Lookahead legalization based global placement for heterogeneous FPGAs","authors":"Sharbani Purkayastha, S. Mukherjee","doi":"10.1109/ISED.2017.8303929","DOIUrl":"https://doi.org/10.1109/ISED.2017.8303929","url":null,"abstract":"With increasing size and complexity of FPGA, placement has lately become the main concern in FPGA physical design. The existing approaches use both packing and placement technique for FPGA placement separately. Unlike the existing methods, we propose a novel global placement approach for heterogeneous FPGA without undergoing packing. The focus of the work is to find the global placement of heterogeneous FPGA architecture with minimum wire length. The existing FPGA placement algorithms first consider packing the logic elements, LUTs and FFs into BLEs then place it in a target FPGA architecture. The proposed global placement approach avoids packing thereby removes the overhead of packing phase in FPGA design. The proposed method consists of (1) Clustering, (2) Fixed block (I/O) placement, (3) Window selection, (4)Placing hard blocks using lookahead legalization.(5) Placing soft blocks using lookahead legalization. The proposed algorithm is evaluated and tested on ISPD 2016 benchmark circuits. The obtained results are found at par with the results of other existing techniques with respect to total wire length.","PeriodicalId":147019,"journal":{"name":"2017 7th International Symposium on Embedded Computing and System Design (ISED)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133393566","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/ISED.2017.8303943
Meelu Padhi, R. Chaudhari
Real time applications of digital communication systems are rapidly increasing. Due to this there is a huge demand for high level of security. In cryptographic algorithms, SHA-256 has become an integral part in many applications. A hardware implementation of the SHA-256 hash algorithm is physically separate from the main processor and hence, it has more security and higher performance than the software implementation. An execution of a hash algorithm on FPGAs is convenient, as it is flexible and easily upgradable. However, implementation of this algorithm on hardware has been challenging, due to the demand of high processing speed. In this paper, an optimized pipelined architecture of SHA-256 hash function has been implemented in hardware HDL Verilog language and synthesized in Xilinx Virtex-4 FPGA. The compressor and expander block of hash function are modified. Carry skip adder is also used to improve the performance of the architecture. The obtained result shows a significant improvement in the performance of the proposed SHA-256 algorithm and it is compared with existing various architectures. Its maximum clock frequency is 170.75 MHz, throughput of 1344.98 Mbps and an improved efficiency of 2.2 Mbps/ slice.
{"title":"An optimized pipelined architecture of SHA-256 hash function","authors":"Meelu Padhi, R. Chaudhari","doi":"10.1109/ISED.2017.8303943","DOIUrl":"https://doi.org/10.1109/ISED.2017.8303943","url":null,"abstract":"Real time applications of digital communication systems are rapidly increasing. Due to this there is a huge demand for high level of security. In cryptographic algorithms, SHA-256 has become an integral part in many applications. A hardware implementation of the SHA-256 hash algorithm is physically separate from the main processor and hence, it has more security and higher performance than the software implementation. An execution of a hash algorithm on FPGAs is convenient, as it is flexible and easily upgradable. However, implementation of this algorithm on hardware has been challenging, due to the demand of high processing speed. In this paper, an optimized pipelined architecture of SHA-256 hash function has been implemented in hardware HDL Verilog language and synthesized in Xilinx Virtex-4 FPGA. The compressor and expander block of hash function are modified. Carry skip adder is also used to improve the performance of the architecture. The obtained result shows a significant improvement in the performance of the proposed SHA-256 algorithm and it is compared with existing various architectures. Its maximum clock frequency is 170.75 MHz, throughput of 1344.98 Mbps and an improved efficiency of 2.2 Mbps/ slice.","PeriodicalId":147019,"journal":{"name":"2017 7th International Symposium on Embedded Computing and System Design (ISED)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122740665","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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