{"title":"Testing and verification of HDL-models for SoC components","authors":"V. Hahanov, I. Hahanova, C. U. Ngene, T. Yves","doi":"10.1109/EWDTS.2010.5742112","DOIUrl":null,"url":null,"abstract":"The testing and verification technology for system HDL models, focused to the significant improvement of the quality of design components for digital systems on chips and reduction the development time (time-to-market) by using the simulation environment, testable analysis of the logical structure HDL-program and the optimal placement of assertion engine is proposed.","PeriodicalId":405223,"journal":{"name":"2010 East-West Design & Test Symposium (EWDTS)","volume":"303 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 East-West Design & Test Symposium (EWDTS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EWDTS.2010.5742112","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
The testing and verification technology for system HDL models, focused to the significant improvement of the quality of design components for digital systems on chips and reduction the development time (time-to-market) by using the simulation environment, testable analysis of the logical structure HDL-program and the optimal placement of assertion engine is proposed.
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