Pub Date : 2010-09-17DOI: 10.1109/EWDTS.2010.5742078
M. Haghbayan, Z. Navabi
In this paper we present an architecture and corresponding algorithm for bus testing in the System on Chip (SoC) design. In our test methodology we used hierarchical functional testing to test all available components in a bus except cores of the SoC as fast as possible. According to our proposed method, first small components and wires are tested and then, higher level operations of the bus (like burst transfers) will be tested. For each step of bus testing, an architecture is proposed. We show the efficiency of our proposed method using a real SoC as experimental result.
{"title":"Architecture design and technical methodology for bus testing","authors":"M. Haghbayan, Z. Navabi","doi":"10.1109/EWDTS.2010.5742078","DOIUrl":"https://doi.org/10.1109/EWDTS.2010.5742078","url":null,"abstract":"In this paper we present an architecture and corresponding algorithm for bus testing in the System on Chip (SoC) design. In our test methodology we used hierarchical functional testing to test all available components in a bus except cores of the SoC as fast as possible. According to our proposed method, first small components and wires are tested and then, higher level operations of the bus (like burst transfers) will be tested. For each step of bus testing, an architecture is proposed. We show the efficiency of our proposed method using a real SoC as experimental result.","PeriodicalId":405223,"journal":{"name":"2010 East-West Design & Test Symposium (EWDTS)","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125560674","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-09-17DOI: 10.1109/EWDTS.2010.5742047
Andrey Zakonov, Oleg A. Stepanov, A. Shalyto
Extended Finite State Machines (EFSMs) are often used in model-based development and for modeling VHDL specifications. This paper proposes an approach for automated test generation for EFSM models. Design by contract approach is applied to formalize specification requirements. Genetic algorithm is proposed to find set of values that triggers given path in the EFSM and reveals inconsistensies with the specification.
{"title":"GA-based and design by contract approach to test generation for EFSMs","authors":"Andrey Zakonov, Oleg A. Stepanov, A. Shalyto","doi":"10.1109/EWDTS.2010.5742047","DOIUrl":"https://doi.org/10.1109/EWDTS.2010.5742047","url":null,"abstract":"Extended Finite State Machines (EFSMs) are often used in model-based development and for modeling VHDL specifications. This paper proposes an approach for automated test generation for EFSM models. Design by contract approach is applied to formalize specification requirements. Genetic algorithm is proposed to find set of values that triggers given path in the EFSM and reveals inconsistensies with the specification.","PeriodicalId":405223,"journal":{"name":"2010 East-West Design & Test Symposium (EWDTS)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126742784","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-09-17DOI: 10.1109/EWDTS.2010.5742119
Aditi Kajala, G. Sinsinwar, R. Choudhary, Jaynarayan T. Tudu, Virendra Singh
Multiple copies of the same functional units are common in today's design. It allows us to reduce golden reference storage by performing comparison of output response of the identical circuits when identical input sequence is applied to them. We present output response comparison scheme for identical sequential circuits for delay test using static transition probability. This allows us to make selection independent of the input sequence.
{"title":"On selection of state variables for delay test of identical functional units","authors":"Aditi Kajala, G. Sinsinwar, R. Choudhary, Jaynarayan T. Tudu, Virendra Singh","doi":"10.1109/EWDTS.2010.5742119","DOIUrl":"https://doi.org/10.1109/EWDTS.2010.5742119","url":null,"abstract":"Multiple copies of the same functional units are common in today's design. It allows us to reduce golden reference storage by performing comparison of output response of the identical circuits when identical input sequence is applied to them. We present output response comparison scheme for identical sequential circuits for delay test using static transition probability. This allows us to make selection independent of the input sequence.","PeriodicalId":405223,"journal":{"name":"2010 East-West Design & Test Symposium (EWDTS)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122621939","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-09-17DOI: 10.1109/EWDTS.2010.5742127
V. Hahanov, A. Hahanova, Vagan Zakaryan
This article describes a high-speed technology for description and solving logical problems, using the Boolean graphs of associative tables, by means of hardware implementation of parallel synthesis and analysis of algebraic, graph and tabular structures of predicate relations for obtaining deterministic multivalued result in n-dimensional discrete space. The problems of creating a theory of brain-like calculations are considered in the form: a metric of associative relations, association description architecture, optimization of the logical data structures, predicate computing models of system-level, architecture and instruction set of logical associative multiprocessor, synthesis and analysis of adjectives [1–5].
{"title":"Cyber space evolution","authors":"V. Hahanov, A. Hahanova, Vagan Zakaryan","doi":"10.1109/EWDTS.2010.5742127","DOIUrl":"https://doi.org/10.1109/EWDTS.2010.5742127","url":null,"abstract":"This article describes a high-speed technology for description and solving logical problems, using the Boolean graphs of associative tables, by means of hardware implementation of parallel synthesis and analysis of algebraic, graph and tabular structures of predicate relations for obtaining deterministic multivalued result in n-dimensional discrete space. The problems of creating a theory of brain-like calculations are considered in the form: a metric of associative relations, association description architecture, optimization of the logical data structures, predicate computing models of system-level, architecture and instruction set of logical associative multiprocessor, synthesis and analysis of adjectives [1–5].","PeriodicalId":405223,"journal":{"name":"2010 East-West Design & Test Symposium (EWDTS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129867558","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-09-17DOI: 10.1109/EWDTS.2010.5742048
M. Jenihhin, J. Raik, R. Ubar, T. Shchenova
The paper presents an approach for assertion coverage analysis targeted at quality assessment of simulation-based verification stimuli and design error debug. The approach considers high-level decision diagrams based design verification flow and relies on temporally extended high-level decision diagrams for PSL assertion representation. The discussed case study illustrates the advantages of the proposed idea.
{"title":"An approach for PSL assertion coverage analysis with high-level decision diagrams","authors":"M. Jenihhin, J. Raik, R. Ubar, T. Shchenova","doi":"10.1109/EWDTS.2010.5742048","DOIUrl":"https://doi.org/10.1109/EWDTS.2010.5742048","url":null,"abstract":"The paper presents an approach for assertion coverage analysis targeted at quality assessment of simulation-based verification stimuli and design error debug. The approach considers high-level decision diagrams based design verification flow and relies on temporally extended high-level decision diagrams for PSL assertion representation. The discussed case study illustrates the advantages of the proposed idea.","PeriodicalId":405223,"journal":{"name":"2010 East-West Design & Test Symposium (EWDTS)","volume":"138 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128720236","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-09-17DOI: 10.1109/EWDTS.2010.5742080
D. Melnik, O. Lukashenko, S. A. Zaychenko
The number of independent clock domains found on the typical today's device is continuously growing. According to the latest industry research, the average number of clock domains on a single device is >15–20 and it becomes higher and higher from day to day. The CDC-related design flaws are also growing exponentially, appearing to be very dangerous as the roots of intermittent chip failures (can be found only in the silicon). Static CDC verification is considered as one of the first de-facto steps in today's SoC design methodology; only static techniques can work as soon as the RTL starts taking shape [1]. This paper discusses early detection of potentially missing synchronizers on clock domain crossing paths, using structural static analysis.
{"title":"Early detection of potentially non-synchronized CDC paths using structural analysis technique","authors":"D. Melnik, O. Lukashenko, S. A. Zaychenko","doi":"10.1109/EWDTS.2010.5742080","DOIUrl":"https://doi.org/10.1109/EWDTS.2010.5742080","url":null,"abstract":"The number of independent clock domains found on the typical today's device is continuously growing. According to the latest industry research, the average number of clock domains on a single device is >15–20 and it becomes higher and higher from day to day. The CDC-related design flaws are also growing exponentially, appearing to be very dangerous as the roots of intermittent chip failures (can be found only in the silicon). Static CDC verification is considered as one of the first de-facto steps in today's SoC design methodology; only static techniques can work as soon as the RTL starts taking shape [1]. This paper discusses early detection of potentially missing synchronizers on clock domain crossing paths, using structural static analysis.","PeriodicalId":405223,"journal":{"name":"2010 East-West Design & Test Symposium (EWDTS)","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130359285","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-09-17DOI: 10.1109/EWDTS.2010.5742118
A. Adamov, V. Hahanov
This paper describes a problem of trust in hardware that can be compromised by means of malicious inclusions called Hardware Trojans. The Hardware Trojans can be embedded in safety critical, security and military systems, such as weapon control systems, battlefield communication systems, information collection and decision making systems, satellite electronics, banking systems, cryptosystems, etc. The goal of the paper is to represent potential abilities of Trojan implementation in integrated circuits (IC) as well as the formal description of Trojan model and probable ways of security verification at a high level of data abstraction.
{"title":"Security risks in hardware: Implementation and detection problem","authors":"A. Adamov, V. Hahanov","doi":"10.1109/EWDTS.2010.5742118","DOIUrl":"https://doi.org/10.1109/EWDTS.2010.5742118","url":null,"abstract":"This paper describes a problem of trust in hardware that can be compromised by means of malicious inclusions called Hardware Trojans. The Hardware Trojans can be embedded in safety critical, security and military systems, such as weapon control systems, battlefield communication systems, information collection and decision making systems, satellite electronics, banking systems, cryptosystems, etc. The goal of the paper is to represent potential abilities of Trojan implementation in integrated circuits (IC) as well as the formal description of Trojan model and probable ways of security verification at a high level of data abstraction.","PeriodicalId":405223,"journal":{"name":"2010 East-West Design & Test Symposium (EWDTS)","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116500092","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-09-17DOI: 10.1109/EWDTS.2010.5742134
V. Pavlenko, V. Burdeinyi
This paper is devoted to the transparent parallelizing technology. It describes the questions that arise while implementing a framework based on this technology. Architecture of such framework is shown and functionality of its parts is described. Efficiency of the implemented framework is shown by parallelizing a sample problem.
{"title":"Cluster computing framework based on transparent parallelizing technology","authors":"V. Pavlenko, V. Burdeinyi","doi":"10.1109/EWDTS.2010.5742134","DOIUrl":"https://doi.org/10.1109/EWDTS.2010.5742134","url":null,"abstract":"This paper is devoted to the transparent parallelizing technology. It describes the questions that arise while implementing a framework based on this technology. Architecture of such framework is shown and functionality of its parts is described. Efficiency of the implemented framework is shown by parallelizing a sample problem.","PeriodicalId":405223,"journal":{"name":"2010 East-West Design & Test Symposium (EWDTS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128033385","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-09-17DOI: 10.1109/EWDTS.2010.5742097
Vazgen Melikyan, K. Sahakyan, A. Nazaryan
A cascaded power clamp technique is proposed for mixed-voltage IC's power pins ESD protection using 65nm 2.5V salicided transistors for dual well processes. The effective power-to-ground cascade ESD clamp circuits for mixed 2.5V and 5V powers have been designed to provide low-impedance path between mixed powers and ground lines of IC during the ESD stress. The stacked power clamp also can be used only for 5V power supply without any electrical overstress on transistors. The discussed ESD protection method is easy simulate able and allow having predictable HBM ESD level. The HBM level of this clamp is up to 5kV with allowable layout area.
{"title":"5V tolerant power clamps for mixed-voltage IC's in 65nm 2.5V salicided CMOS technology","authors":"Vazgen Melikyan, K. Sahakyan, A. Nazaryan","doi":"10.1109/EWDTS.2010.5742097","DOIUrl":"https://doi.org/10.1109/EWDTS.2010.5742097","url":null,"abstract":"A cascaded power clamp technique is proposed for mixed-voltage IC's power pins ESD protection using 65nm 2.5V salicided transistors for dual well processes. The effective power-to-ground cascade ESD clamp circuits for mixed 2.5V and 5V powers have been designed to provide low-impedance path between mixed powers and ground lines of IC during the ESD stress. The stacked power clamp also can be used only for 5V power supply without any electrical overstress on transistors. The discussed ESD protection method is easy simulate able and allow having predictable HBM ESD level. The HBM level of this clamp is up to 5kV with allowable layout area.","PeriodicalId":405223,"journal":{"name":"2010 East-West Design & Test Symposium (EWDTS)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125956994","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-09-17DOI: 10.1109/EWDTS.2010.5742137
J. Sosnowski
The paper presents our experience with developing tests for microcontroller based embedded systems. We use application specific tests. They are integrated with the implemented application (program) and available on-line error detection mechanisms. The effectiveness of this approach has been analyzed in simulation experiments and referenced to some practical problem in embedded systems.
{"title":"Self-testing of microcontrollers in the field","authors":"J. Sosnowski","doi":"10.1109/EWDTS.2010.5742137","DOIUrl":"https://doi.org/10.1109/EWDTS.2010.5742137","url":null,"abstract":"The paper presents our experience with developing tests for microcontroller based embedded systems. We use application specific tests. They are integrated with the implemented application (program) and available on-line error detection mechanisms. The effectiveness of this approach has been analyzed in simulation experiments and referenced to some practical problem in embedded systems.","PeriodicalId":405223,"journal":{"name":"2010 East-West Design & Test Symposium (EWDTS)","volume":"105 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130039637","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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