Development of /spl delta/B/i-Si//spl delta/Sb and /spl delta/B/i-Si//spl delta/Sb/i-Si//spl delta/B resonant interband tunnel diodes for integrated circuit applications

Abstract

Recent developments in Si based tunnel diode technologies have made the realization of circuits incorporating both tunnel diodes and transistors feasible. A recent study by the authors presented the design of an n-on-p Si RITD layer with a peak-to-valley current ratio (PVCR) of 2.15 at a current density of 3 kA/cm/sup 2/ which was grown by molecular beam epitaxy (MBE) (Thompson et al, Appl. Phys. Lett. vol. 75, pp. 1308-1310, 1999). Further studies of this structure investigated additional tunnel barrier thicknesses of 4 nm, 8 nm, and 10 nm. In all samples, room temperature NDR was observed comparable to that of the baseline 6 nm RITD. Simple adjustments to the tunnel barrier thickness can be made to tailor the performance for a particular circuit application. However, growth of a complimentary p-on-n tunnel diode is problematic due to Sb segregation through the intrinsic tunneling spacer. The solution is to control the Sb segregation by employing multiple substrate temperatures during MBE growth. Following the success of the complementary p-on-n growth strategy, it was now possible to demonstrate the integration of two tunnel diodes in a single growth. The basic flow and design presented here follow that of III-V RITDs (Yang et al, 1995), presenting a symmetric pnp RITD structure. The motivation for developing this structure was to mimic the I-V characteristic of III-V RITDs which have NDR regions under forward and reverse bias. A Si-based structure with these properties would facilitate the development of a Goto-type memory cell (Goto et al, 1960).