Power distribution analysis methodology for a multi-gigabit I/O interface

R. Schmitt, X. Huang, C. Yuan
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引用次数: 2

Abstract

As the operating frequency of I/O circuits increases and voltage swing decreases, it becomes increasingly important to verify the power distribution network (PDN). This paper presents a methodology used to design and verify the PDN for a multi-gigabit memory interfaces. It describes the modeling of PDN components, the necessary analysis steps to assist in the design of a high-quality PDN, and the simulations to predict the impact of supply noise on the signal quality in the memory channel.
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多千兆I/O接口的功率分配分析方法
随着I/O电路工作频率的增加和电压摆幅的减小,对配电网络(PDN)的验证变得越来越重要。本文提出了一种用于设计和验证多千兆存储接口的PDN的方法。它描述了PDN组件的建模,辅助高质量PDN设计的必要分析步骤,以及预测电源噪声对存储通道中信号质量影响的仿真。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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