Pub Date : 2003-12-08DOI: 10.1109/EPEP.2003.1249995
J. Ihm, A. Cangellaris
A methodology is presented for on-chip power grid modeling with uncompromised electromagnetic accuracy. The proposed methodology avoids the painstaking and error-prone process of power grid inductance extraction. Furthermore, the model is developed directly from the differential form of Maxwell's equations, and thus avoids the dense-matrix issues that arise when PEEC-based electromagnetic models are utilized. Finally, it has the unique attribute that, in addition to providing for on-chip power switching modeling with electromagnetic accuracy it enables the direct modeling of distributed power-grid induced electromagnetic interference.
{"title":"Distributed on-chip power grid modeling: an electromagnetic alternative to RLC extraction-based models","authors":"J. Ihm, A. Cangellaris","doi":"10.1109/EPEP.2003.1249995","DOIUrl":"https://doi.org/10.1109/EPEP.2003.1249995","url":null,"abstract":"A methodology is presented for on-chip power grid modeling with uncompromised electromagnetic accuracy. The proposed methodology avoids the painstaking and error-prone process of power grid inductance extraction. Furthermore, the model is developed directly from the differential form of Maxwell's equations, and thus avoids the dense-matrix issues that arise when PEEC-based electromagnetic models are utilized. Finally, it has the unique attribute that, in addition to providing for on-chip power switching modeling with electromagnetic accuracy it enables the direct modeling of distributed power-grid induced electromagnetic interference.","PeriodicalId":254477,"journal":{"name":"Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127252747","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/EPEP.2003.1250041
H. Heck, S. Hall, B. Horine, K. Mallory, T. Wig
Phase skew in high speed differential signals caused by local spatial variation in dielectric constant is presented. A simple mathematical model that allows estimation of the impact on multi-Gb/s signaling links is developed, along with HSpice models that correlate to frequency domain measurements. Options for mitigating the impacts are also discussed.
{"title":"Impact of FR4 dielectric non-uniformity on the performance of multi-Gb/s differential signals","authors":"H. Heck, S. Hall, B. Horine, K. Mallory, T. Wig","doi":"10.1109/EPEP.2003.1250041","DOIUrl":"https://doi.org/10.1109/EPEP.2003.1250041","url":null,"abstract":"Phase skew in high speed differential signals caused by local spatial variation in dielectric constant is presented. A simple mathematical model that allows estimation of the impact on multi-Gb/s signaling links is developed, along with HSpice models that correlate to frequency domain measurements. Options for mitigating the impacts are also discussed.","PeriodicalId":254477,"journal":{"name":"Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128333006","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/EPEP.2003.1250025
B. Young
To address the need for package models in the earliest project stages before package layout has even begun, a package description language and a package model synthesizer have been developed and are described.
{"title":"Package model synthesis","authors":"B. Young","doi":"10.1109/EPEP.2003.1250025","DOIUrl":"https://doi.org/10.1109/EPEP.2003.1250025","url":null,"abstract":"To address the need for package models in the earliest project stages before package layout has even begun, a package description language and a package model synthesizer have been developed and are described.","PeriodicalId":254477,"journal":{"name":"Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128495956","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/EPEP.2003.1250002
R. Ito, R. Jackson
A two dimensional frequency domain transmission line matrix method (TLM) is used to model a parallel plate environment (or power-ground plane) with a slot which radiates into free space. A simple method of moments is employed to model the slot radiation in conjunction with TLM. A via wall waveguide with a slot is used as a test vehicle and results are compared to measurements.
{"title":"Parallel plate waveguide with radiating slot modeling using two dimensional frequency domain transmission line matrix method","authors":"R. Ito, R. Jackson","doi":"10.1109/EPEP.2003.1250002","DOIUrl":"https://doi.org/10.1109/EPEP.2003.1250002","url":null,"abstract":"A two dimensional frequency domain transmission line matrix method (TLM) is used to model a parallel plate environment (or power-ground plane) with a slot which radiates into free space. A simple method of moments is employed to model the slot radiation in conjunction with TLM. A via wall waveguide with a slot is used as a test vehicle and results are compared to measurements.","PeriodicalId":254477,"journal":{"name":"Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129192028","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/EPEP.2003.1249990
A. Norman, D. Shykind, M. Falconer, K. Ruffer
A new method for validating interconnect performance has been demonstrated. The use of DOE permitted timely acquisition of data by optimizing the number of experiments (measurements) needed. The model fitting (RSM) of the data allowed for confident prediction across all high volume conditions, even though every case could not be tested. There were a number of new learnings and huge extensions to the ability to understand and characterize bus performance. One key learning was that buffer compensation works very well. Note that the edge rate at the receiver shows little variation across all measured conditions. In addition, the RSM models predict very little impact to setup/hold margins due to process and temperature. The RSM models also showed that motherboard length, motherboard impedance, and termination voltage have the most impact on FSB performance. This correlates very well with simulated interconnect results.
{"title":"Application of Design of Experiments (DOE) methods to high-speed interconnect validation","authors":"A. Norman, D. Shykind, M. Falconer, K. Ruffer","doi":"10.1109/EPEP.2003.1249990","DOIUrl":"https://doi.org/10.1109/EPEP.2003.1249990","url":null,"abstract":"A new method for validating interconnect performance has been demonstrated. The use of DOE permitted timely acquisition of data by optimizing the number of experiments (measurements) needed. The model fitting (RSM) of the data allowed for confident prediction across all high volume conditions, even though every case could not be tested. There were a number of new learnings and huge extensions to the ability to understand and characterize bus performance. One key learning was that buffer compensation works very well. Note that the edge rate at the receiver shows little variation across all measured conditions. In addition, the RSM models predict very little impact to setup/hold margins due to process and temperature. The RSM models also showed that motherboard length, motherboard impedance, and termination voltage have the most impact on FSB performance. This correlates very well with simulated interconnect results.","PeriodicalId":254477,"journal":{"name":"Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123684600","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/EPEP.2003.1250069
Zhaohui Zhu, S. Dvorak, J. Prince
In this paper, a method of moments (MoM) based, full-wave layered interconnect simulator, UA-FWLIS is extended to handle interconnects with bends. The accuracy of this new bend-cell expansion function is investigated by comparing with Agilent Momentum.
{"title":"Efficient full-wave analysis of packaging interconnects with bends using the method of moments","authors":"Zhaohui Zhu, S. Dvorak, J. Prince","doi":"10.1109/EPEP.2003.1250069","DOIUrl":"https://doi.org/10.1109/EPEP.2003.1250069","url":null,"abstract":"In this paper, a method of moments (MoM) based, full-wave layered interconnect simulator, UA-FWLIS is extended to handle interconnects with bends. The accuracy of this new bend-cell expansion function is investigated by comparing with Agilent Momentum.","PeriodicalId":254477,"journal":{"name":"Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116512388","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/EPEP.2003.1250039
A. Deutsch, T. Winkel, G. Kopcsay, C. Surovic, B. Rubin, G. Katopis, B. Chamberlin
The self-consistent frequency-dependent dielectric constant, /spl epsiv//sub r/(f), and dielectric loss, tan/spl delta/(f), are determined over the range 2 to 30 GHz using a short-pulse propagation technique and an iterative extraction based on a rational function expansion. Simulations of signal propagation on printed circuit board wiring using transmission-line models based on these results show very good agreement with measured step and pulse time-domain excitations.
{"title":"Extraction of /spl epsiv/(f) and tan /spl delta/(f) for BT insulator up to 30 GHz using the short-pulse propagation technique","authors":"A. Deutsch, T. Winkel, G. Kopcsay, C. Surovic, B. Rubin, G. Katopis, B. Chamberlin","doi":"10.1109/EPEP.2003.1250039","DOIUrl":"https://doi.org/10.1109/EPEP.2003.1250039","url":null,"abstract":"The self-consistent frequency-dependent dielectric constant, /spl epsiv//sub r/(f), and dielectric loss, tan/spl delta/(f), are determined over the range 2 to 30 GHz using a short-pulse propagation technique and an iterative extraction based on a rational function expansion. Simulations of signal propagation on printed circuit board wiring using transmission-line models based on these results show very good agreement with measured step and pulse time-domain excitations.","PeriodicalId":254477,"journal":{"name":"Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124388788","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/EPEP.2003.1249999
X. Duo, Lirong Zheng, H. Tenhunen
In this paper, we present common emitter LNAs (low noise amplifiers) in system-on-package for 5GHz WLAN application. Innovation of this module is that it is chip-package co-designed and co-simulated with performance trade-offs for on-chip versus off-chip passive component integration. It thus provides an optimal total solution for embedded RF electronics in system-level integration. Analytical equations for key performance parameters, noise figure and gain, of these LNAs are developed as functions of quality factors of passive components and the package parasitics. They hence provide designers a quantitative trade-off for on-chip versus off chip passive components integration in Sod design. The final module is composed of on-chip active components in 0.5/spl mu/m SiGe BiCMOS technology and off-chip passive components integrated in MCM-D substrate. Significant improvement in performance is found in these co-designed LNAs than those in single-chip LNAs.
{"title":"Chip-package co-design of common emitter LNA in system-on-package with on-chip versus off-chip passive component analysis","authors":"X. Duo, Lirong Zheng, H. Tenhunen","doi":"10.1109/EPEP.2003.1249999","DOIUrl":"https://doi.org/10.1109/EPEP.2003.1249999","url":null,"abstract":"In this paper, we present common emitter LNAs (low noise amplifiers) in system-on-package for 5GHz WLAN application. Innovation of this module is that it is chip-package co-designed and co-simulated with performance trade-offs for on-chip versus off-chip passive component integration. It thus provides an optimal total solution for embedded RF electronics in system-level integration. Analytical equations for key performance parameters, noise figure and gain, of these LNAs are developed as functions of quality factors of passive components and the package parasitics. They hence provide designers a quantitative trade-off for on-chip versus off chip passive components integration in Sod design. The final module is composed of on-chip active components in 0.5/spl mu/m SiGe BiCMOS technology and off-chip passive components integrated in MCM-D substrate. Significant improvement in performance is found in these co-designed LNAs than those in single-chip LNAs.","PeriodicalId":254477,"journal":{"name":"Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124162024","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/EPEP.2003.1250071
Chuanyi Yang, G. Ouyang, V. Jandhyala
A full-wave time domain integral equation formulation for the simulation of finite conductors and dielectrics, linked to linear and non-linear lumped elements, is presented. The method permits coupled rigorous simulation including accounting for EMI and non-linearities in the presence of material effects. In addition, a new quadrature scheme is incorporated for exactly computing temporal delays between every section of finite basis functions defined over triangular patches. This enables finer time step resolution for non-uniform meshes than is permissible with standard Gaussian quadrature and singularity extraction.
{"title":"Integral equation based time domain coupled EM-circuit simulation for packaged conductors and dielectrics","authors":"Chuanyi Yang, G. Ouyang, V. Jandhyala","doi":"10.1109/EPEP.2003.1250071","DOIUrl":"https://doi.org/10.1109/EPEP.2003.1250071","url":null,"abstract":"A full-wave time domain integral equation formulation for the simulation of finite conductors and dielectrics, linked to linear and non-linear lumped elements, is presented. The method permits coupled rigorous simulation including accounting for EMI and non-linearities in the presence of material effects. In addition, a new quadrature scheme is incorporated for exactly computing temporal delays between every section of finite basis functions defined over triangular patches. This enables finer time step resolution for non-uniform meshes than is permissible with standard Gaussian quadrature and singularity extraction.","PeriodicalId":254477,"journal":{"name":"Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132298912","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/EPEP.2003.1250004
U. Pfeiffer, A. Chandrasekhar
We have shown the variation of the RF performance of the QFN package in accordance with its high volume manufacturing and assembly process. We have also developed a distributed model for the chip-to-package interconnect.
{"title":"Statistical analysis and modelling of low-cost leadless packages for wireless applications based on non-destructive measurements","authors":"U. Pfeiffer, A. Chandrasekhar","doi":"10.1109/EPEP.2003.1250004","DOIUrl":"https://doi.org/10.1109/EPEP.2003.1250004","url":null,"abstract":"We have shown the variation of the RF performance of the QFN package in accordance with its high volume manufacturing and assembly process. We have also developed a distributed model for the chip-to-package interconnect.","PeriodicalId":254477,"journal":{"name":"Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134077924","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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