{"title":"Improving the gate oxide integrity of very high voltage MCT and IGBT devices by external gettering of metal impurities","authors":"E. Herr, H. Baltes, U. Thiemann, T. Stockmeier","doi":"10.1109/ISPSD.1994.583725","DOIUrl":null,"url":null,"abstract":"We observed that gate oxides of MCT and IGBT devices exhibited lower breakdown field strengths when the devices were fabricated on float-zone (FZ) instead of Czochralski-grown (CZ) silicon starting material. This is because of the different precipitation behavior of heavy metal contaminants. Using neutron activation analysis (NAA), we determined Fe and Ni concentration levels that weaken the gate oxides of BiMOS devices on FZ silicon. We compared the effect of various external gettering techniques on the gate oxide integrity. External gettering by polysilicon layers and by argon implantation damage were employed on the wafer back to improve the gate oxide integrity of BiMOS devices fabricated on FZ material.","PeriodicalId":405897,"journal":{"name":"Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"1994-05-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISPSD.1994.583725","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
We observed that gate oxides of MCT and IGBT devices exhibited lower breakdown field strengths when the devices were fabricated on float-zone (FZ) instead of Czochralski-grown (CZ) silicon starting material. This is because of the different precipitation behavior of heavy metal contaminants. Using neutron activation analysis (NAA), we determined Fe and Ni concentration levels that weaken the gate oxides of BiMOS devices on FZ silicon. We compared the effect of various external gettering techniques on the gate oxide integrity. External gettering by polysilicon layers and by argon implantation damage were employed on the wafer back to improve the gate oxide integrity of BiMOS devices fabricated on FZ material.
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