Pub Date : 1994-05-31DOI: 10.1109/ISPSD.1994.583727
H. Matsuda, T. Fujiwara, M. Hiyoshi, K. Nishitani, A. Kuwako, T. Ikehara
GTOs suddenly failed without any leakage current increase before the failure event, during DC voltage blocking. From various experiments and the analysis, we have come to the inference that the GTO failure was caused by cosmic-rays at sea level. The failure rate of the improved GTOs decreases by more than one order.
{"title":"Analysis of GTO failure mode during DC voltage blocking","authors":"H. Matsuda, T. Fujiwara, M. Hiyoshi, K. Nishitani, A. Kuwako, T. Ikehara","doi":"10.1109/ISPSD.1994.583727","DOIUrl":"https://doi.org/10.1109/ISPSD.1994.583727","url":null,"abstract":"GTOs suddenly failed without any leakage current increase before the failure event, during DC voltage blocking. From various experiments and the analysis, we have come to the inference that the GTO failure was caused by cosmic-rays at sea level. The failure rate of the improved GTOs decreases by more than one order.","PeriodicalId":405897,"journal":{"name":"Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1994-05-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127272277","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-31DOI: 10.1109/ISPSD.1994.583700
Y. Baba, S. Yanagiya, Y. Koshino, Y. Udo
Silicon direct bonding and deep trench techniques are a good combination for high density and high voltage ICs such as display drivers. High voltage devices in these ICs are perfectly isolated by thick SOI oxide and isolation trenches. The SOI oxide thickness increases the blocking voltage of full depletion devices. On the other hand, it increases the warpage of SOI wafers and makes troubles in handling them. The new trench drain structure solves these problems and provides high voltage, low ON resistance LDMOS-FET. Its drain-source blocking voltage is 290 V, and the ON resistance is 0.37 /spl Omega/cm/sup 2/ including the isolation area.
{"title":"High voltage trench drain LDMOS-FET using SOI wafer","authors":"Y. Baba, S. Yanagiya, Y. Koshino, Y. Udo","doi":"10.1109/ISPSD.1994.583700","DOIUrl":"https://doi.org/10.1109/ISPSD.1994.583700","url":null,"abstract":"Silicon direct bonding and deep trench techniques are a good combination for high density and high voltage ICs such as display drivers. High voltage devices in these ICs are perfectly isolated by thick SOI oxide and isolation trenches. The SOI oxide thickness increases the blocking voltage of full depletion devices. On the other hand, it increases the warpage of SOI wafers and makes troubles in handling them. The new trench drain structure solves these problems and provides high voltage, low ON resistance LDMOS-FET. Its drain-source blocking voltage is 290 V, and the ON resistance is 0.37 /spl Omega/cm/sup 2/ including the isolation area.","PeriodicalId":405897,"journal":{"name":"Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1994-05-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126113893","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-31DOI: 10.1109/ISPSD.1994.583751
F. Udrea, G. Amaratunga
A novel MOS-controlled power device termed the Inversion Layer Emitter Thyristor (ILET) is proposed. The principle of operation is based on a new physical concept that expresses the transition of an inversion layer from a majority carrier channel into a minority carrier injector. The device operates in a combined thyristor-IGBT mode having the thyristor emitter formed by an inversion layer. In the on-state the effective channel of the MOS structure is of sub-micrometre order, and does not affect the off-state voltage blocking capability of the device.
{"title":"The inversion layer emitter thyristor - a novel power device concept","authors":"F. Udrea, G. Amaratunga","doi":"10.1109/ISPSD.1994.583751","DOIUrl":"https://doi.org/10.1109/ISPSD.1994.583751","url":null,"abstract":"A novel MOS-controlled power device termed the Inversion Layer Emitter Thyristor (ILET) is proposed. The principle of operation is based on a new physical concept that expresses the transition of an inversion layer from a majority carrier channel into a minority carrier injector. The device operates in a combined thyristor-IGBT mode having the thyristor emitter formed by an inversion layer. In the on-state the effective channel of the MOS structure is of sub-micrometre order, and does not affect the off-state voltage blocking capability of the device.","PeriodicalId":405897,"journal":{"name":"Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1994-05-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122373518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-31DOI: 10.1109/ISPSD.1994.583656
S. P. Robb, A.A. Taomoto, S. Tu
Short circuit protection can be provided for IGBTs by using a current-sensing scheme. The performance and accuracy of integrated current sensors on IGBTs can be affected by the layout of the sense device. Data is presented on current-sense IGBTs and an improved layout is proposed to increase the accuracy of the sensor.
{"title":"Current sensing in IGBTs for short-circuit protection","authors":"S. P. Robb, A.A. Taomoto, S. Tu","doi":"10.1109/ISPSD.1994.583656","DOIUrl":"https://doi.org/10.1109/ISPSD.1994.583656","url":null,"abstract":"Short circuit protection can be provided for IGBTs by using a current-sensing scheme. The performance and accuracy of integrated current sensors on IGBTs can be affected by the layout of the sense device. Data is presented on current-sense IGBTs and an improved layout is proposed to increase the accuracy of the sensor.","PeriodicalId":405897,"journal":{"name":"Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1994-05-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116247717","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-31DOI: 10.1109/ISPSD.1994.583776
Y. Li, C. Salama, M. Seufert, M. King
The design and implementation of high-voltage MOS transistors fully compatible with 0.8 /spl mu/m BICMOS technology is considered in this paper. Two-dimensional simulations were used in the design of the structures. Three different structures are presented. The results indicate that it is possible to implement MOS devices with a pitch of 8 /spl mu/m, breakdown voltage of the order of 20 to 50 V and specific on-resistance of the order of 0.8 to 10 m/spl Omega/ cm/sup 2/ by minor layout modifications and without changes in the process itself.
{"title":"Submicron BICMOS compatible high voltage MOS transistors","authors":"Y. Li, C. Salama, M. Seufert, M. King","doi":"10.1109/ISPSD.1994.583776","DOIUrl":"https://doi.org/10.1109/ISPSD.1994.583776","url":null,"abstract":"The design and implementation of high-voltage MOS transistors fully compatible with 0.8 /spl mu/m BICMOS technology is considered in this paper. Two-dimensional simulations were used in the design of the structures. Three different structures are presented. The results indicate that it is possible to implement MOS devices with a pitch of 8 /spl mu/m, breakdown voltage of the order of 20 to 50 V and specific on-resistance of the order of 0.8 to 10 m/spl Omega/ cm/sup 2/ by minor layout modifications and without changes in the process itself.","PeriodicalId":405897,"journal":{"name":"Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1994-05-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121464487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-31DOI: 10.1109/ISPSD.1994.583627
H. Dettmer, W. Fichtner, F. Bauer
MOS controlled thyristors (MCTs) with 4.5 kV static blocking voltage have been fabricated and characterized. A buffer layer with anode shorts has been adapted to the conventional MCT structure to reach the high blocking voltage together with a low on-state voltage. Three different cathode designs with varying emitter area, turn-on channel width and turn-off channel width, have been realized. These IMCTs show MOS controlled turn-on at anode voltages as low as 2.2 V. The on-state voltage is 1.6 V at 100 A cm/sup -2/. The leakage current of these devices is less than 2/spl middot/10/sup -5/ A cm/sup -2/ at room temperature and 4.5 kV blocking voltage. It was demonstrated that these MCTs are able to turn off a current density of 50 A cm/sup -2/ at a line voltage of 3.5 kV in 10 /spl mu/s under inductive load without any snubber, thereby producing a turn-off energy density of approximately 0.7 Jcm/sup -2/.
{"title":"4.5 kV MCT with buffer layer and anode short structure","authors":"H. Dettmer, W. Fichtner, F. Bauer","doi":"10.1109/ISPSD.1994.583627","DOIUrl":"https://doi.org/10.1109/ISPSD.1994.583627","url":null,"abstract":"MOS controlled thyristors (MCTs) with 4.5 kV static blocking voltage have been fabricated and characterized. A buffer layer with anode shorts has been adapted to the conventional MCT structure to reach the high blocking voltage together with a low on-state voltage. Three different cathode designs with varying emitter area, turn-on channel width and turn-off channel width, have been realized. These IMCTs show MOS controlled turn-on at anode voltages as low as 2.2 V. The on-state voltage is 1.6 V at 100 A cm/sup -2/. The leakage current of these devices is less than 2/spl middot/10/sup -5/ A cm/sup -2/ at room temperature and 4.5 kV blocking voltage. It was demonstrated that these MCTs are able to turn off a current density of 50 A cm/sup -2/ at a line voltage of 3.5 kV in 10 /spl mu/s under inductive load without any snubber, thereby producing a turn-off energy density of approximately 0.7 Jcm/sup -2/.","PeriodicalId":405897,"journal":{"name":"Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1994-05-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134298266","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-31DOI: 10.1109/ISPSD.1994.583737
J. Vobecký, P. Hazdra, J. Voves, F. Spurný, J. Homola
Both the ion and electron irradiation of power devices have already become a widely used practice to locally reduce the minority carrier lifetime. For efficient and accurate design of irradiation parameters, i.e. ion type, irradiation energy and dose, annealing temperature, etc., the device simulation taking into account the fully characterized deep levels and solving the complete solution of trap-dynamic equations is necessary.
{"title":"Accurate simulation of combined electron and ion irradiated silicon devices for local lifetime tailoring","authors":"J. Vobecký, P. Hazdra, J. Voves, F. Spurný, J. Homola","doi":"10.1109/ISPSD.1994.583737","DOIUrl":"https://doi.org/10.1109/ISPSD.1994.583737","url":null,"abstract":"Both the ion and electron irradiation of power devices have already become a widely used practice to locally reduce the minority carrier lifetime. For efficient and accurate design of irradiation parameters, i.e. ion type, irradiation energy and dose, annealing temperature, etc., the device simulation taking into account the fully characterized deep levels and solving the complete solution of trap-dynamic equations is necessary.","PeriodicalId":405897,"journal":{"name":"Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1994-05-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131588500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-31DOI: 10.1109/ISPSD.1994.583652
V. Parthasarathy, K. So, Z. Shen, T. Chow
The impact of cell design on the safe operating area (SOA) of n-channel IGBTs is assessed. It is shown that the atomic layer lattice (ALL) cell geometry is important for improving the latchup dominated SOA of 500 V n-channel IGBTs. Experimental results for the latchup performance of n-channel ALL cell IGBTs, presented for the first time, show that even at a temperature of 200/spl deg/C these devices do not latch at all but are instead current limited. The experimental measurements and tradeoffs for the different cell geometries have been found to corroborate the trends in the numerical simulations.
{"title":"Cell optimization for 500 V n-channel IGBTs","authors":"V. Parthasarathy, K. So, Z. Shen, T. Chow","doi":"10.1109/ISPSD.1994.583652","DOIUrl":"https://doi.org/10.1109/ISPSD.1994.583652","url":null,"abstract":"The impact of cell design on the safe operating area (SOA) of n-channel IGBTs is assessed. It is shown that the atomic layer lattice (ALL) cell geometry is important for improving the latchup dominated SOA of 500 V n-channel IGBTs. Experimental results for the latchup performance of n-channel ALL cell IGBTs, presented for the first time, show that even at a temperature of 200/spl deg/C these devices do not latch at all but are instead current limited. The experimental measurements and tradeoffs for the different cell geometries have been found to corroborate the trends in the numerical simulations.","PeriodicalId":405897,"journal":{"name":"Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1994-05-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132082148","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-31DOI: 10.1109/ISPSD.1994.583616
T. Yamada, G. Majumdar, S. Mori, H. Hagino, H. Kondoh, T. Hirao
A brief history of power semiconductors, starting from its bipolar based origin to the state-of-art Intelligent Power Modules (IPMs), has been briefly reviewed at first, and is followed by an analysis of the changing requirements from the application fields. In accordance with it, next generation IPMs with new concepts have been proposed. The next generation IPMs are expected to grow in two specific directions. One is a growth toward a high power zone where performance enhancement by use of new IGBT structure and additional protection would be essential. Second is a growth toward low power zone where an ASIC-like system integration approach by use of new HVICs and packaging would be essential.
{"title":"Next generation power module","authors":"T. Yamada, G. Majumdar, S. Mori, H. Hagino, H. Kondoh, T. Hirao","doi":"10.1109/ISPSD.1994.583616","DOIUrl":"https://doi.org/10.1109/ISPSD.1994.583616","url":null,"abstract":"A brief history of power semiconductors, starting from its bipolar based origin to the state-of-art Intelligent Power Modules (IPMs), has been briefly reviewed at first, and is followed by an analysis of the changing requirements from the application fields. In accordance with it, next generation IPMs with new concepts have been proposed. The next generation IPMs are expected to grow in two specific directions. One is a growth toward a high power zone where performance enhancement by use of new IGBT structure and additional protection would be essential. Second is a growth toward low power zone where an ASIC-like system integration approach by use of new HVICs and packaging would be essential.","PeriodicalId":405897,"journal":{"name":"Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1994-05-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130873004","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-31DOI: 10.1109/ISPSD.1994.583733
R. Singh, B. J. Baliga
The results of detailed measurements, simulations and modeling on 500 V, 4 Amps NPN BJTs are reported in the 300-77 K temperature range. For these devices, as the operating temperature is reduced from 300 to 77 K, the current gain has been found to decrease by more than an order of magnitude; the on-state collector-emitter and base-emitter voltages increase by 40 and 80% respectively; although the collector-base breakdown decreases by about 20%, the collector-emitter breakdown increases by about 20%, and the storage and fall times reduce by 10/spl times/ and 6/spl times/, respectively. Through numerical simulations it is shown that the emitter current crowding is much more severe at 77 K than at 300 K. Using verified analytical models and established optimization techniques, it is shown that a 77 K optimally designed BJT has a lower emitter, base and collector dopings and a larger emitter area than a similarly rated 300 K optimized device.
{"title":"Cryogenic operation of power bipolar transistors","authors":"R. Singh, B. J. Baliga","doi":"10.1109/ISPSD.1994.583733","DOIUrl":"https://doi.org/10.1109/ISPSD.1994.583733","url":null,"abstract":"The results of detailed measurements, simulations and modeling on 500 V, 4 Amps NPN BJTs are reported in the 300-77 K temperature range. For these devices, as the operating temperature is reduced from 300 to 77 K, the current gain has been found to decrease by more than an order of magnitude; the on-state collector-emitter and base-emitter voltages increase by 40 and 80% respectively; although the collector-base breakdown decreases by about 20%, the collector-emitter breakdown increases by about 20%, and the storage and fall times reduce by 10/spl times/ and 6/spl times/, respectively. Through numerical simulations it is shown that the emitter current crowding is much more severe at 77 K than at 300 K. Using verified analytical models and established optimization techniques, it is shown that a 77 K optimally designed BJT has a lower emitter, base and collector dopings and a larger emitter area than a similarly rated 300 K optimized device.","PeriodicalId":405897,"journal":{"name":"Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1994-05-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125541641","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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