Fabrication Of Nanometer Scale Structure Using Thin Film Stress

Abstract

I . I n t r o d u c t i o n For many applications u l t r a f i n e s t ructures have been fabricated by opt ical lithography, dry etching, AFM machining tool and electron beam lithography. However these methods need high cos t and complicated process for la rge scale process. I n t h e past we have reported on nanometer scale formation with 20 nm gap based on polysilicon layer"'. Now we w i l l present a simple nanometer scale formation technique with s i l i c o n layer and w i l l e lucidate the formation mechanism. 11. Experiment A schematic diagram of the key fabrication process f o r wedge type nanostructure is presented i n Figure l ( a ) . A Si3N4 layer of 1600 A was deposited by LPCM a t 700 -C on SIMOX wafer with 4000 A-thick-SiOz. After photolithography pat terning of the electrodes, which were i n i t i a l l y merged, the Si& and Si layers were etched by dry etching The bottom Si02 layer was p a r t i a l l y etched under control, and the samples were annealed i n N2 ambient with the various temperature and t h e time. Figure l (b) shows the schematic view of fabr icated wedge type s t ruc ture with gap. The gap was formed a t the minimum cross sect ion area of the patterned wedge by stress which had been generated during annealing and cooling. Figure 2 shows the qua l i ta t ive dis t r ibut ion of the s t r e s s i n each layer formed during the annealing process"'. The compressive stress formed i n each layers f i n a l l y a c t a s a tens i le stress a t the minimum cross sect ion area of s t ructure . If the t e n s i l e thermal stress was large, the merged area was s p l i t t e d i n t o two par t and formed a gap between them, Figure 3 shows the gap spacing with annealing time evolution a t 1100 "C a f t e r l a t e r a l l y 2 pm and 11 pm Si02 etching. The gap was saturated about 250 nm and a b u t 190 nm f o r 2 ,um and 11 pm Si02 etching respectively. The gap width of 30 samples measured was within *lox of average saturation value. I t was thought tha t the difference of the gaps between the two l a t e r a l Si02 etching conditions was caused by the f a c t tha t the Si02 layer act a s repulsive force for tensi le thermal stress a t minimum cross section area. Figure 4 shows the scanning electron microscopy (SEMI photography of typical fabr icated nanostructure with about 250 nm gap which was formed a f t e r annealing a t 1100 'C for 1 hour Conclusion We fabricated the s i l i con nanostructure wi th nanometer sca le gap using thin film s t r e s s The gap width which was formed i n the layers during thermal annealing a t high temperature could be controlled by annealing temperature and annealing time.