Dampening high frequency noise in high performance microprocessor packaging

T. Arabi, G. Ji, G. Taylor
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引用次数: 4

Abstract

In high performance microprocessors, power supply noise needs to be controlled to ensure reliable high speed bus operation. This is generally done with high quality package capacitors and on die capacitance. These capacitors are generally lower equivalent series inductance (ESL) and lower equivalent series resistor (ESR). Because the ESL is not zero, die capacitance is required to reduce the impact of this ESL on the power supply noise. Alternatively, in this paper, we present a novel approach of using an on-die metal resistor in series with the package capacitance to dampen the high frequency noise. We show by validation on the 90 nm technology that this technique is capable of reducing the noise by nearly 80% without adversely affecting the bus speed.
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抑制高性能微处理器封装中的高频噪声
在高性能微处理器中,为了保证高速总线的可靠运行,需要对电源噪声进行控制。这通常是用高质量的封装电容器和片上电容完成的。这些电容器一般是低等效串联电感(ESL)和低等效串联电阻(ESR)。由于ESL不为零,因此需要使用晶片电容来降低该ESL对电源噪声的影响。另外,在本文中,我们提出了一种使用片上金属电阻与封装电容串联的新方法来抑制高频噪声。我们通过对90纳米技术的验证表明,该技术能够在不影响总线速度的情况下将噪声降低近80%。
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Presentation of a new time domain simulation tool and application to the analysis of advanced interconnect performance dependence on design and process parameters Sensitivity analysis of generic on-chip /spl Delta/I-noise simulation methodology A frequency domain approach for efficient model reduction of mixed VLSI circuits Non-uniform grid (NG) algorithm for fast capacitance extraction Dampening high frequency noise in high performance microprocessor packaging
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