Pub Date : 2004-05-09DOI: 10.1109/SPI.2004.1409012
M.F. Ktata, H. Grabinski, U. Arz, H. Fischer
The influence of the ground line position on the signal shape in the time domain is investigated in the presence of grounded substrates by M. F. Ktata et al. (2003) with different conductivities of 10 S/m (low) and 100 S/m (medium). It is shown that the impact of substrate effects on time domain signals depends on the substrate conductivity, on the relative position of the ground line with respect to the signal lines as well as on the length of the line system. In addition, the impact of process-related generated voids between closely spaced signal lines on crosstalk is investigated, too.
m . F. Ktata等人(2003)研究了在接地基板存在的情况下，地线位置对时域信号形状的影响，其电导率分别为10 S/m(低)和100 S/m(中)。结果表明，衬底效应对时域信号的影响取决于衬底电导率、地线相对于信号线的相对位置以及线路系统的长度。此外，还研究了紧密间隔的信号线之间与工艺相关的产生的空隙对串扰的影响。
{"title":"Crosstalk in product related bus systems using 110 nm CMOS technology","authors":"M.F. Ktata, H. Grabinski, U. Arz, H. Fischer","doi":"10.1109/SPI.2004.1409012","DOIUrl":"https://doi.org/10.1109/SPI.2004.1409012","url":null,"abstract":"The influence of the ground line position on the signal shape in the time domain is investigated in the presence of grounded substrates by M. F. Ktata et al. (2003) with different conductivities of 10 S/m (low) and 100 S/m (medium). It is shown that the impact of substrate effects on time domain signals depends on the substrate conductivity, on the relative position of the ground line with respect to the signal lines as well as on the length of the line system. In addition, the impact of process-related generated voids between closely spaced signal lines on crosstalk is investigated, too.","PeriodicalId":119776,"journal":{"name":"Proceedings. 8th IEEE Workshop on Signal Propagation on Interconnects","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121024683","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-09DOI: 10.1109/SPI.2004.1409024
A. Ligocka, W. Bandurski
In the paper the analytical formula for the propagation delay of CMOS gate driving a distributed RLC line was derived. It is shown that obtained formula is more accurate in some cases than used in literature. The main idea of the presented approach is based on the expansion of the voltage unit step response into Taylor series. The coefficients of this expansion are calculated in symbolical manner in frequency domain as the moments determined for infinite frequency.
{"title":"Effect of inductance on interconnect propagation delay in VLSI circuits","authors":"A. Ligocka, W. Bandurski","doi":"10.1109/SPI.2004.1409024","DOIUrl":"https://doi.org/10.1109/SPI.2004.1409024","url":null,"abstract":"In the paper the analytical formula for the propagation delay of CMOS gate driving a distributed RLC line was derived. It is shown that obtained formula is more accurate in some cases than used in literature. The main idea of the presented approach is based on the expansion of the voltage unit step response into Taylor series. The coefficients of this expansion are calculated in symbolical manner in frequency domain as the moments determined for infinite frequency.","PeriodicalId":119776,"journal":{"name":"Proceedings. 8th IEEE Workshop on Signal Propagation on Interconnects","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127178267","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-09DOI: 10.1109/SPI.2004.1409044
A. Hekkala, T. Tarvainen
High speed data transmission is now required in many applications. One limiting factor on speed can be radiated emissions. This paper presents simulation and measurement results on electromagnetic leakage of various differential cable connector assemblies. Leakage modelling aspects are also considered. Differential and common mode interferences as well as single and double shielded assemblies where grounding pin number directly connected to the cable screen varies are studied. The research methods are FIT simulations and absorbing clamp measurements. It is shown that the symmetry of the differential shielding is important and to suppress common mode interferences high amount of grounding pins is required when unscreened connectors like typical high-speed digital ones are used. Double shielded assemblies leak much less.
{"title":"Screening attenuation of differential cable-connector assemblies","authors":"A. Hekkala, T. Tarvainen","doi":"10.1109/SPI.2004.1409044","DOIUrl":"https://doi.org/10.1109/SPI.2004.1409044","url":null,"abstract":"High speed data transmission is now required in many applications. One limiting factor on speed can be radiated emissions. This paper presents simulation and measurement results on electromagnetic leakage of various differential cable connector assemblies. Leakage modelling aspects are also considered. Differential and common mode interferences as well as single and double shielded assemblies where grounding pin number directly connected to the cable screen varies are studied. The research methods are FIT simulations and absorbing clamp measurements. It is shown that the symmetry of the differential shielding is important and to suppress common mode interferences high amount of grounding pins is required when unscreened connectors like typical high-speed digital ones are used. Double shielded assemblies leak much less.","PeriodicalId":119776,"journal":{"name":"Proceedings. 8th IEEE Workshop on Signal Propagation on Interconnects","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129739555","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-09DOI: 10.1109/SPI.2004.1409050
Y. Quéré, T. Le Gouguec, P. Martin, D. Le Berre, F. Huret
The mode conversion means that a modification of the electromagnetic field configuration occurs, generally, after discontinuities. In deep submicron digital ULSI circuits, the mode conversion analysis is indispensable to identify the signal return path, the return current distribution and therefore, for an accurate inductance modelling which remains a challenging problem (Y. I. Ismael and E. G. Friedman, 2000). On the other hand, switching activity of high speed CMOS circuit may produce large current derivatives in wires (crosstalk) and substrate. These current transients can generate large potential surges and coupled noise. In this mind, a reduction of the mode conversion phenomenon decreases noise in high speed ULSI circuits (Y. Quere et al., 2003). We have investigated the mode conversion, in the frequency domain, for multiple-line inter-layer transitions in CMOS devices. The signal integrity analysis in time domain proved the detrimental effects of mode conversion. Finally, we confirmed that our design rule reduces the mode conversion phenomenon in the case of transition with multiple coupled lines.
模式转换通常是指在不连续之后发生电磁场结构的改变。在深亚微米数字ULSI电路中，模式转换分析对于识别信号返回路径，返回电流分布以及因此精确的电感建模是必不可少的，这仍然是一个具有挑战性的问题(Y. I. Ismael和E. G. Friedman, 2000)。另一方面，高速CMOS电路的开关活动可能会在导线(串扰)和衬底中产生较大的电流导数。这些电流瞬态会产生较大的电位浪涌和耦合噪声。在这种思想中，减少模式转换现象可以降低高速ULSI电路中的噪声(Y. Quere等人，2003)。我们研究了CMOS器件中多线层间跃迁的频域模式转换。时域信号完整性分析证明了模式转换的不利影响。最后，我们证实了我们的设计规则减少了多耦合线过渡情况下的模式转换现象。
{"title":"Effects of mode conversion on parasitic coupling in high-speed VLSI circuits","authors":"Y. Quéré, T. Le Gouguec, P. Martin, D. Le Berre, F. Huret","doi":"10.1109/SPI.2004.1409050","DOIUrl":"https://doi.org/10.1109/SPI.2004.1409050","url":null,"abstract":"The mode conversion means that a modification of the electromagnetic field configuration occurs, generally, after discontinuities. In deep submicron digital ULSI circuits, the mode conversion analysis is indispensable to identify the signal return path, the return current distribution and therefore, for an accurate inductance modelling which remains a challenging problem (Y. I. Ismael and E. G. Friedman, 2000). On the other hand, switching activity of high speed CMOS circuit may produce large current derivatives in wires (crosstalk) and substrate. These current transients can generate large potential surges and coupled noise. In this mind, a reduction of the mode conversion phenomenon decreases noise in high speed ULSI circuits (Y. Quere et al., 2003). We have investigated the mode conversion, in the frequency domain, for multiple-line inter-layer transitions in CMOS devices. The signal integrity analysis in time domain proved the detrimental effects of mode conversion. Finally, we confirmed that our design rule reduces the mode conversion phenomenon in the case of transition with multiple coupled lines.","PeriodicalId":119776,"journal":{"name":"Proceedings. 8th IEEE Workshop on Signal Propagation on Interconnects","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129793736","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-09DOI: 10.1109/SPI.2004.1409043
A. Amghayrir, P. Bréhonnet, N. Tanguy, P. Vilbé, L. Calvez, F. Huret
It has become well accepted that interconnect delay dominates gate delay in current VLSI circuits. This paper introduces a new method, based on a frequency domain approach, for the simulation of interconnect problems found in high speed digital circuits and SOC-AMS.
{"title":"A frequency domain approach for efficient model reduction of mixed VLSI circuits","authors":"A. Amghayrir, P. Bréhonnet, N. Tanguy, P. Vilbé, L. Calvez, F. Huret","doi":"10.1109/SPI.2004.1409043","DOIUrl":"https://doi.org/10.1109/SPI.2004.1409043","url":null,"abstract":"It has become well accepted that interconnect delay dominates gate delay in current VLSI circuits. This paper introduces a new method, based on a frequency domain approach, for the simulation of interconnect problems found in high speed digital circuits and SOC-AMS.","PeriodicalId":119776,"journal":{"name":"Proceedings. 8th IEEE Workshop on Signal Propagation on Interconnects","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114370487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-09DOI: 10.1109/SPI.2004.1409051
G. Becherini, A. Musolino, M. Raugi
In this paper a method to determine upper and lower bounds for crosstalk signals in interconnects is presented. Assuming a quasi TEM propagation interconnects are modeled as transmission lines whose equivalent circuit is considered. From the frequency response of the equivalent circuit the dependence of the far end voltages on lines parameter is derived and the interval of variation is determined. Considering uncertain geometric characteristic of a simplified but meaningful geometry results have been obtained showing that the derived bounds accurately confine the actual space of variation of the crosstalk signals.
{"title":"Crosstalk bounds in interconnects with random parameters","authors":"G. Becherini, A. Musolino, M. Raugi","doi":"10.1109/SPI.2004.1409051","DOIUrl":"https://doi.org/10.1109/SPI.2004.1409051","url":null,"abstract":"In this paper a method to determine upper and lower bounds for crosstalk signals in interconnects is presented. Assuming a quasi TEM propagation interconnects are modeled as transmission lines whose equivalent circuit is considered. From the frequency response of the equivalent circuit the dependence of the far end voltages on lines parameter is derived and the interval of variation is determined. Considering uncertain geometric characteristic of a simplified but meaningful geometry results have been obtained showing that the derived bounds accurately confine the actual space of variation of the crosstalk signals.","PeriodicalId":119776,"journal":{"name":"Proceedings. 8th IEEE Workshop on Signal Propagation on Interconnects","volume":"250 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132495180","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-09DOI: 10.1109/SPI.2004.1409047
V. Kondratyev
An efficient and simple method of modelling of printed-circuit board (PCB) discontinuities is presented. Based on time-domain measurements and subsequent microwave analysis the method enables the PCB discontinuity S-parameters to be calculated. Then, as black box, they can be incorporated into a circuit simulator in order to carry out the transient analysis of overall digital module. The modelling results of DIN-connector are compared to experimental data and good agreement is reported.
{"title":"On the modelling of interconnection discontinuities","authors":"V. Kondratyev","doi":"10.1109/SPI.2004.1409047","DOIUrl":"https://doi.org/10.1109/SPI.2004.1409047","url":null,"abstract":"An efficient and simple method of modelling of printed-circuit board (PCB) discontinuities is presented. Based on time-domain measurements and subsequent microwave analysis the method enables the PCB discontinuity S-parameters to be calculated. Then, as black box, they can be incorporated into a circuit simulator in order to carry out the transient analysis of overall digital module. The modelling results of DIN-connector are compared to experimental data and good agreement is reported.","PeriodicalId":119776,"journal":{"name":"Proceedings. 8th IEEE Workshop on Signal Propagation on Interconnects","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133745216","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-09DOI: 10.1109/SPI.2004.1409052
G. Sommer, W. John, H. Reichl
The integration of passive components onto a module platform offers great potential for miniaturization of RF and microwave systems. Development of component design with respect to electrical requirements is one of the challenges in RF system design. This paper first introduces a layout synthesis algorithm for embedded passive components like capacitor, resistor and inductor. For required electrical parameter of embedded passives (main values) including RF characteristic (resonant frequency, quality factor, 3dB cutoff frequency) the optimized component layout are generated. For electrical simulation respective s-parameter and equivalent circuit model are derived. This synthesis procedure is a break through for modern RF system design. The synthesis algorithm is universal and can be applied easily for various design types of embedded inductors, capacitors and resistors. The method is demonstrated using HDI organic square loop inductors as a specific example.
{"title":"Layout synthesis algorithm of embedded passive components for RF and EMC reliable system design","authors":"G. Sommer, W. John, H. Reichl","doi":"10.1109/SPI.2004.1409052","DOIUrl":"https://doi.org/10.1109/SPI.2004.1409052","url":null,"abstract":"The integration of passive components onto a module platform offers great potential for miniaturization of RF and microwave systems. Development of component design with respect to electrical requirements is one of the challenges in RF system design. This paper first introduces a layout synthesis algorithm for embedded passive components like capacitor, resistor and inductor. For required electrical parameter of embedded passives (main values) including RF characteristic (resonant frequency, quality factor, 3dB cutoff frequency) the optimized component layout are generated. For electrical simulation respective s-parameter and equivalent circuit model are derived. This synthesis procedure is a break through for modern RF system design. The synthesis algorithm is universal and can be applied easily for various design types of embedded inductors, capacitors and resistors. The method is demonstrated using HDI organic square loop inductors as a specific example.","PeriodicalId":119776,"journal":{"name":"Proceedings. 8th IEEE Workshop on Signal Propagation on Interconnects","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115211333","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-09DOI: 10.1109/SPI.2004.1409037
I. Doerr, G. Sommer, H. Reichl
A novel approach for electrical modeling of multiple coupled wire bonds up to a frequency of 10GHz is presented. This paper describes a very easy way to get complex electrical model for complex structures like multiple coupled wire bonds. Electromagnetic field computation and compact model extraction using optimization algorithm is limited on few elements. A very efficient way is starting with the development of an equivalent circuit model for a single wire bond. The electrical model of single interconnect is used to model coupled interconnects. Full wave electromagnetic field computation was used to calculate the S-parameters. S-parameters are very good suitable to extract compact models for radio frequencies (RF). Moreover, this procedure is still more effectively by using parameterized models for design kits and libraries.
{"title":"A novel modeling approach for multiple coupled wire bond interconnects","authors":"I. Doerr, G. Sommer, H. Reichl","doi":"10.1109/SPI.2004.1409037","DOIUrl":"https://doi.org/10.1109/SPI.2004.1409037","url":null,"abstract":"A novel approach for electrical modeling of multiple coupled wire bonds up to a frequency of 10GHz is presented. This paper describes a very easy way to get complex electrical model for complex structures like multiple coupled wire bonds. Electromagnetic field computation and compact model extraction using optimization algorithm is limited on few elements. A very efficient way is starting with the development of an equivalent circuit model for a single wire bond. The electrical model of single interconnect is used to model coupled interconnects. Full wave electromagnetic field computation was used to calculate the S-parameters. S-parameters are very good suitable to extract compact models for radio frequencies (RF). Moreover, this procedure is still more effectively by using parameterized models for design kits and libraries.","PeriodicalId":119776,"journal":{"name":"Proceedings. 8th IEEE Workshop on Signal Propagation on Interconnects","volume":"02 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129303624","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-09DOI: 10.1109/SPI.2004.1409045
Y. Hur, C. Chun, M. Maeng, H. Kim, S. Chandramouli, E. Gebara, J. Laskar
This paper demonstrates an active near-end crosstalk (NEXT) noise canceller intended for use in commercial backplanes. Optimum system architecture and specifications are generated using measured channel data. Additionally, CMOS circuit implementation approaches are introduced and their performances are discussed. The NEXT canceller is applied to a 20Gbps 4-PAM signal over a 16-inch backplane channel and shows 75% cancellation.
{"title":"A 0.18/spl mu/m-CMOS near-end crosstalk (NEXT) noise canceller for 4-PAM/20Gbps throughput transmission over backplane channels","authors":"Y. Hur, C. Chun, M. Maeng, H. Kim, S. Chandramouli, E. Gebara, J. Laskar","doi":"10.1109/SPI.2004.1409045","DOIUrl":"https://doi.org/10.1109/SPI.2004.1409045","url":null,"abstract":"This paper demonstrates an active near-end crosstalk (NEXT) noise canceller intended for use in commercial backplanes. Optimum system architecture and specifications are generated using measured channel data. Additionally, CMOS circuit implementation approaches are introduced and their performances are discussed. The NEXT canceller is applied to a 20Gbps 4-PAM signal over a 16-inch backplane channel and shows 75% cancellation.","PeriodicalId":119776,"journal":{"name":"Proceedings. 8th IEEE Workshop on Signal Propagation on Interconnects","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131126255","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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