Haiying Ma, Ligang Lu, Haitao Qian, Jing Han, Xin Wen, Fanjin Meng, Rahul Singhal, Martin Keim, Yu Huang, Wu Yang
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引用次数: 1
Abstract
Complex application specific SoC are being developed for hardware support artificial intelligence (AI) applications. Such a complex SoCs are integrating a large number of on-chip and off-chip memories, numerous cores and interfaces including in our case a hierarchy of embedded TAPs, as well as security measures and Design-For-Test (DFT) structures. In this case-study paper, we demonstrate using IEEE 1687-2014 (IJTAG) to integrate all these different components into a single, unifying methodology. From this, we derive the benefits of workflow efficiency and fast silicon bring-up. For example, we can report that silicon bring-up of the DFT of the entire SoC was completed in about 4 days, and other bring-up aspects of the Soc were also completed in very little time.