Digital Lithography for Advanced Packaging and Heterogenous Integration

Abstract

As heterogeneous integration is increasingly adopted for semiconductor development and innovation, back-end lithography requirements are growing. More redistribution layers (RDLs) within the package are driving the need for finer RDL line/spacing (L/S) as well as smaller critical dimensions for micro-bumps and micro-pillars. In this work, digital lithography was used to demonstrate an efficient dual damascene process implementation with respect to RDL and interconnect scaling. Multi-level exposure was used to reduce 50 % of lithographic steps and to allow for simultaneous generation of RDL and via structures without alignment. The results showed well-defined patterns with lateral dimensions < 5 µm which enable a new manufacturing scheme for the dual-damascene process with significant reduction in complexity and process time.