Pub Date : 2022-12-07DOI: 10.1109/EPTC56328.2022.10013256
R. Ooi, F. Costa, Sam Hsieh, E. Chiu, Wendy Xu, Dave Yu, Darwin Fan, Allen Cheng, Andrew Gattuso, Yongfu Wang, Currey Hsieh, Jeffery Toran, J. Thompson, Pierre-Louis Toussaint, Ryan Curry, L. W. Keat, R. Kulterman, H. Fu
High density interconnect (HDI) sockets for CPU, GPU etc. is trending to larger form factor as the interconnect counts approach the realm of 10,000. One of the key bottleneck in HDI socket development is the ability of flow and warpage simulation techniques to reduce the design cycle time. The focus of this project is to explore novel simulation techniques to speed up the flow prediction part of simulation and reduce physical experiments needed to improve time to market (TTM) cycle of HDI sockets. The main challenge in HDI socket simulation is: (1) complexity of fibre-filled liquid crystal polymer (LCP) material properties and (2) complex but repetitive pin holes in the core pin region of the HDI socket. This takes up ~90% of the simulation time and slows down the design cycle. In this project, focus was put in to simplify the repetitive pin hole structure. The pin hole arrays are represented by equivalent flow resistant model and produce similar flow patterns in shorter time. In order to achieve this, three (3) LCP materials grades with known properties were provided by project partner Celanese. Test vehicle (TV) of HDI sockets were then build by socket fabrication partners using the LCP material provided. Room temp (RT) warpage of the socket were measured, together with short-shot samples collected for simulation flow and warpage prediction validation. The repetitive pin hole arrays of the HDI sockets are represented by equivalent flow resistant model. The predicted flow patterns from simulation are in good agreement with short-shot samples. The warpage shape and magnitude predictions are also in good agreement for 2 out of 3 material grades. It was later found out that the odd material that has different warpage has a different matrix (resin) LCP property. Solving time improvement ranging between 3.6x and 35x times were demonstrated in the proof of concept. The project outcome allows faster flow and warpage simulation for HDI socket design and development. The utilization of numerical predictions will be greatly increased, reduced material cost used for design prototyping and injection mold chase tape outs. Simulation software partners from the project will develop further on the demo beta versions for eventual product releases.
{"title":"High Density Interconnect (HDI) Socket Flow & Waprage Prediction & Characterization","authors":"R. Ooi, F. Costa, Sam Hsieh, E. Chiu, Wendy Xu, Dave Yu, Darwin Fan, Allen Cheng, Andrew Gattuso, Yongfu Wang, Currey Hsieh, Jeffery Toran, J. Thompson, Pierre-Louis Toussaint, Ryan Curry, L. W. Keat, R. Kulterman, H. Fu","doi":"10.1109/EPTC56328.2022.10013256","DOIUrl":"https://doi.org/10.1109/EPTC56328.2022.10013256","url":null,"abstract":"High density interconnect (HDI) sockets for CPU, GPU etc. is trending to larger form factor as the interconnect counts approach the realm of 10,000. One of the key bottleneck in HDI socket development is the ability of flow and warpage simulation techniques to reduce the design cycle time. The focus of this project is to explore novel simulation techniques to speed up the flow prediction part of simulation and reduce physical experiments needed to improve time to market (TTM) cycle of HDI sockets. The main challenge in HDI socket simulation is: (1) complexity of fibre-filled liquid crystal polymer (LCP) material properties and (2) complex but repetitive pin holes in the core pin region of the HDI socket. This takes up ~90% of the simulation time and slows down the design cycle. In this project, focus was put in to simplify the repetitive pin hole structure. The pin hole arrays are represented by equivalent flow resistant model and produce similar flow patterns in shorter time. In order to achieve this, three (3) LCP materials grades with known properties were provided by project partner Celanese. Test vehicle (TV) of HDI sockets were then build by socket fabrication partners using the LCP material provided. Room temp (RT) warpage of the socket were measured, together with short-shot samples collected for simulation flow and warpage prediction validation. The repetitive pin hole arrays of the HDI sockets are represented by equivalent flow resistant model. The predicted flow patterns from simulation are in good agreement with short-shot samples. The warpage shape and magnitude predictions are also in good agreement for 2 out of 3 material grades. It was later found out that the odd material that has different warpage has a different matrix (resin) LCP property. Solving time improvement ranging between 3.6x and 35x times were demonstrated in the proof of concept. The project outcome allows faster flow and warpage simulation for HDI socket design and development. The utilization of numerical predictions will be greatly increased, reduced material cost used for design prototyping and injection mold chase tape outs. Simulation software partners from the project will develop further on the demo beta versions for eventual product releases.","PeriodicalId":163034,"journal":{"name":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125293428","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-07DOI: 10.1109/EPTC56328.2022.10013134
Seok–Phyo Tchun, Joo–Yeop Kim, A. Raj
In the electronic packaging industry, for the past few decades, ENEPIG(Electroless Nickel Electroless Palladium Immersion Gold) plating method has been already widely used for substrates of many different LGA and BGA packages. However, because of chronic quality issues of laminate manufacturing process such as discoloration and corrosion induced from very long process time of Nickel layer plating process, there is a strong demand from laminate substrate suppliers of changing the Nickel layer thickness range from thick 3∼8um to thin 0.08∼0.2um, In this study, we tried to verify the board level reliability performance of Thin Nickel plating ENEPIG laminate packages, comparing with current Thick Nickel plating ENEPIG laminate packages, also compared the performance between LGA and BGA packages.
{"title":"Board-level Reliability Performance Comparison of Thin and Thick Ni plating ENEPIG Laminate LGA and BGA Packages","authors":"Seok–Phyo Tchun, Joo–Yeop Kim, A. Raj","doi":"10.1109/EPTC56328.2022.10013134","DOIUrl":"https://doi.org/10.1109/EPTC56328.2022.10013134","url":null,"abstract":"In the electronic packaging industry, for the past few decades, ENEPIG(Electroless Nickel Electroless Palladium Immersion Gold) plating method has been already widely used for substrates of many different LGA and BGA packages. However, because of chronic quality issues of laminate manufacturing process such as discoloration and corrosion induced from very long process time of Nickel layer plating process, there is a strong demand from laminate substrate suppliers of changing the Nickel layer thickness range from thick 3∼8um to thin 0.08∼0.2um, In this study, we tried to verify the board level reliability performance of Thin Nickel plating ENEPIG laminate packages, comparing with current Thick Nickel plating ENEPIG laminate packages, also compared the performance between LGA and BGA packages.","PeriodicalId":163034,"journal":{"name":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116559295","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-07DOI: 10.1109/EPTC56328.2022.10013279
H. K. Kannojia, G. Van Steenberge
The semiconductor industry can no longer count on monolithic integration to accomplish the economic benefits of the previous era. Now, new packaging solutions are being adopted to achieve the commercial advantages that were previously met with silicon scaling. The role of heterogeneous integration, especially micro-chiplets, is pivotal in this new era. Several techniques are being investigated to allow for massive but still precise assembly of small semiconductor chiplets, including contact transfer printing, fluidic assembly, and laser-induced forward-transfer (LIFT) printing. In addition to very high transfer rates, laser-based mass transfer offers the advantages of being truly selective, and extremely flexible in terms of dimensions and materials. This study presents a combined approach for micro-chiplet preparation and assembly, with a systematic investigation into the transfer accuracy of 200×200 µm2 Si micro-chiplets as a function of various experimental conditions which would be useful for heterogeneous integration of different micro-chiplets in systems-in-package applications.
{"title":"Laser-Induced Forward Transfer for Assembly of Silicon Micro-Chiplets","authors":"H. K. Kannojia, G. Van Steenberge","doi":"10.1109/EPTC56328.2022.10013279","DOIUrl":"https://doi.org/10.1109/EPTC56328.2022.10013279","url":null,"abstract":"The semiconductor industry can no longer count on monolithic integration to accomplish the economic benefits of the previous era. Now, new packaging solutions are being adopted to achieve the commercial advantages that were previously met with silicon scaling. The role of heterogeneous integration, especially micro-chiplets, is pivotal in this new era. Several techniques are being investigated to allow for massive but still precise assembly of small semiconductor chiplets, including contact transfer printing, fluidic assembly, and laser-induced forward-transfer (LIFT) printing. In addition to very high transfer rates, laser-based mass transfer offers the advantages of being truly selective, and extremely flexible in terms of dimensions and materials. This study presents a combined approach for micro-chiplet preparation and assembly, with a systematic investigation into the transfer accuracy of 200×200 µm2 Si micro-chiplets as a function of various experimental conditions which would be useful for heterogeneous integration of different micro-chiplets in systems-in-package applications.","PeriodicalId":163034,"journal":{"name":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116570994","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-07DOI: 10.1109/EPTC56328.2022.10013209
Long-geng Liu, Bo Wang, Wangyun Li, Yu-bing Gong, K. Pan
In this study, the low cycle shear fatigue performance and fracture behavior of microscale ball grid array (BGA) structure Cu/Sn–3.0Ag–0.5Cu/Cu solder joints with various shear amplitudes were systematically investigated at different current densities by experimental, theoretical methods and finite element analysis. The experimental results showed that the fatigue life of the solder joint decreased with increasing shear amplitude and current density. The descent rate of fatigue life decreased with increasing shear amplitude at the same current density. Moreover, the deterioration of current stressing on the fatigue life of the solder joint was more serious at the lower shear amplitude. In addition, with increasing current density, the solder joint fracture position transitioned from the solder matrix to the solder/IMC layer interface, and the shape of the fracture path shifted from arc-shape to flat-shape.
{"title":"Fatigue performance of Cu/Sn–3.0Ag–0.5Cu/Cu solder joints at different current densities","authors":"Long-geng Liu, Bo Wang, Wangyun Li, Yu-bing Gong, K. Pan","doi":"10.1109/EPTC56328.2022.10013209","DOIUrl":"https://doi.org/10.1109/EPTC56328.2022.10013209","url":null,"abstract":"In this study, the low cycle shear fatigue performance and fracture behavior of microscale ball grid array (BGA) structure Cu/Sn–3.0Ag–0.5Cu/Cu solder joints with various shear amplitudes were systematically investigated at different current densities by experimental, theoretical methods and finite element analysis. The experimental results showed that the fatigue life of the solder joint decreased with increasing shear amplitude and current density. The descent rate of fatigue life decreased with increasing shear amplitude at the same current density. Moreover, the deterioration of current stressing on the fatigue life of the solder joint was more serious at the lower shear amplitude. In addition, with increasing current density, the solder joint fracture position transitioned from the solder matrix to the solder/IMC layer interface, and the shape of the fracture path shifted from arc-shape to flat-shape.","PeriodicalId":163034,"journal":{"name":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122140724","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-07DOI: 10.1109/EPTC56328.2022.10013275
Marcel Sippel, R. Schmidt, M. Käsbauer, M. Sprenger, A. Hensel, J. Franke
The top side interconnection of a power semiconductor by aluminum heavy wire bonds is one key point of failure during operation. State of the art lifetime models mostly focus on the operating conditions of the power module. They can be used to correlate lifetime testing data with application conditions but cannot cover the wide range of design parameters relevant for the development of a power module. An extensive power cycling study was conducted in order to evaluate the additional stress induced in the bond interface on the chip by the wire bond loop, with the main focus being on the load current in the wire bond. A strong correlation between the power loss density in the bond loop and the tested lifetime was found over a wide range of load currents. Additional influence factors, such as the number of stitches, were identified in this study. This data can be used to expand existing lifetime models and make them more relevant for power module design.
{"title":"Influence of Current Density on Wire Bond Lifetime in Active Power Cycling Test","authors":"Marcel Sippel, R. Schmidt, M. Käsbauer, M. Sprenger, A. Hensel, J. Franke","doi":"10.1109/EPTC56328.2022.10013275","DOIUrl":"https://doi.org/10.1109/EPTC56328.2022.10013275","url":null,"abstract":"The top side interconnection of a power semiconductor by aluminum heavy wire bonds is one key point of failure during operation. State of the art lifetime models mostly focus on the operating conditions of the power module. They can be used to correlate lifetime testing data with application conditions but cannot cover the wide range of design parameters relevant for the development of a power module. An extensive power cycling study was conducted in order to evaluate the additional stress induced in the bond interface on the chip by the wire bond loop, with the main focus being on the load current in the wire bond. A strong correlation between the power loss density in the bond loop and the tested lifetime was found over a wide range of load currents. Additional influence factors, such as the number of stitches, were identified in this study. This data can be used to expand existing lifetime models and make them more relevant for power module design.","PeriodicalId":163034,"journal":{"name":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","volume":"14 6 Pt 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116847008","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-07DOI: 10.1109/EPTC56328.2022.10013251
L. Tang, J. Woo, M. Chew, Kenneth Lee, Ting Ta Chi
Covalent wafer-to-wafer bonding is one of the package research fields that requires high quality SiO2 interface from 2 sides of Si wafers. Failure analysis on adhesion problem wafers is to understand the root cause of failures for process enhancement. In this paper, three different sample preparation methods have been used to analyze a covalent wafer-to-wafer bonding delamination issue that was captured in SAM. One simple and useful sample preparation method has been introduced in the paper. With this method, further analysis work can be carried out to provide full information of the defects.
{"title":"Failure Analysis Case Study on Covalent Wafer bonding Delamination","authors":"L. Tang, J. Woo, M. Chew, Kenneth Lee, Ting Ta Chi","doi":"10.1109/EPTC56328.2022.10013251","DOIUrl":"https://doi.org/10.1109/EPTC56328.2022.10013251","url":null,"abstract":"Covalent wafer-to-wafer bonding is one of the package research fields that requires high quality SiO2 interface from 2 sides of Si wafers. Failure analysis on adhesion problem wafers is to understand the root cause of failures for process enhancement. In this paper, three different sample preparation methods have been used to analyze a covalent wafer-to-wafer bonding delamination issue that was captured in SAM. One simple and useful sample preparation method has been introduced in the paper. With this method, further analysis work can be carried out to provide full information of the defects.","PeriodicalId":163034,"journal":{"name":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130489393","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-07DOI: 10.1109/EPTC56328.2022.10013110
W. Seit, S. Chong, S. Lim, B. Sajay
Embedded wafer level packaging technology (eWLP) has gained interest for promoting multi -die packages in small volume with high performance [1]. Several factors such as thermal expansion, mold compound shrinkage and mold-flow will affects the die shift [2]. The eWLP package is getting larger and larger to accommodate multi -dies to further increase the functions of the package. Die with different sizes may experience different die shift magnitude as bigger die has stronger adhesion as compare to die with smaller dimension. Stronger adhesion helps to resist the impact of mold flow during the compression molding process. Ultra-large package indicated that the volume of mold compound inside the package is much higher than those packages with smaller dimension. As such, the impact of mold shrinkage and thermal expansion is greater for ultra large eWLP package. In this paper, we will evaluate the die shift for various die sizes for an ultra-large package of 32.05×26.7mm. And hence a method of optimizing the die shift for the various die size in an ultra-large package is developed in this study. The dies will be picked and placed on a taped carrier and then to be molded. After molding, each die position is measured by using Nikon Confocal tool. The die shift is then determined by subtracting the die position with the designated position. Die shift will be compensated based on graphical x-y plot. The outcome of the die shift will be analysed after compensation and fine tune the die shift if necessary. In summary, we had demonstrated the die shift is less than 15um for 3 different die sizes in an ultra-large eWLP package.
{"title":"Comprehensive Study on Die Shift with Ultra-Large Embedded Multi-Die Wafer Level Packaging","authors":"W. Seit, S. Chong, S. Lim, B. Sajay","doi":"10.1109/EPTC56328.2022.10013110","DOIUrl":"https://doi.org/10.1109/EPTC56328.2022.10013110","url":null,"abstract":"Embedded wafer level packaging technology (eWLP) has gained interest for promoting multi -die packages in small volume with high performance [1]. Several factors such as thermal expansion, mold compound shrinkage and mold-flow will affects the die shift [2]. The eWLP package is getting larger and larger to accommodate multi -dies to further increase the functions of the package. Die with different sizes may experience different die shift magnitude as bigger die has stronger adhesion as compare to die with smaller dimension. Stronger adhesion helps to resist the impact of mold flow during the compression molding process. Ultra-large package indicated that the volume of mold compound inside the package is much higher than those packages with smaller dimension. As such, the impact of mold shrinkage and thermal expansion is greater for ultra large eWLP package. In this paper, we will evaluate the die shift for various die sizes for an ultra-large package of 32.05×26.7mm. And hence a method of optimizing the die shift for the various die size in an ultra-large package is developed in this study. The dies will be picked and placed on a taped carrier and then to be molded. After molding, each die position is measured by using Nikon Confocal tool. The die shift is then determined by subtracting the die position with the designated position. Die shift will be compensated based on graphical x-y plot. The outcome of the die shift will be analysed after compensation and fine tune the die shift if necessary. In summary, we had demonstrated the die shift is less than 15um for 3 different die sizes in an ultra-large eWLP package.","PeriodicalId":163034,"journal":{"name":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124016542","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-07DOI: 10.1109/EPTC56328.2022.10013185
T. Sinani, G. Miskovic
In this work delamination behavior $1,6 mumathrm{m}$ thin AF4 coatings on silicon (Si) and glass (SiO2) substrates were tested by scratch testing. The coatings were deposited by vapor deposition polymerization (VDP) technique on untreated and polished 8-inch Si and SiO2 wafers, with root mean square (RMS) roughness of 4 and 2 nm, respectively. Scratch tests were performed in displacement and load controlled mode, where scratch depths were varied from 1 to $1,6 mumathrm{m}$. The indentation loads and subsequently depths, were varied to observe different delamination features over the penetration depth at the substrate-coating interface. Additionally, the scratches were observed in-situ with scanning electron microscopy (SEM) to better understand the changes in lateral force during the test. The results showed that cohesive failure in AF4 happens before adhesive failure at indentation depths down to $1,4 mumathrm{m}$, At $1,4 mumathrm{m}$ depth we can observe first adhesive failure features on the AF4 coating - SiO2 substrate interface. This shows that the AF4 coating on the SiO2 substrate has a slightly lower adhesion than on the Si substrate. The adhesion failures on both samples start to occur at scratches near the AF4-substrate interface, without chipping on the sides. The results also showed that if the scratch depth is not near the AF4-substrate, only the cohesive failure in AF4 can be seen, which indicates very good adhesion for both samples.
{"title":"Delamination behavior study of AF4 parylene thin films on Si and SiO2 substrates by scratch testing","authors":"T. Sinani, G. Miskovic","doi":"10.1109/EPTC56328.2022.10013185","DOIUrl":"https://doi.org/10.1109/EPTC56328.2022.10013185","url":null,"abstract":"In this work delamination behavior $1,6 mumathrm{m}$ thin AF4 coatings on silicon (Si) and glass (SiO2) substrates were tested by scratch testing. The coatings were deposited by vapor deposition polymerization (VDP) technique on untreated and polished 8-inch Si and SiO2 wafers, with root mean square (RMS) roughness of 4 and 2 nm, respectively. Scratch tests were performed in displacement and load controlled mode, where scratch depths were varied from 1 to $1,6 mumathrm{m}$. The indentation loads and subsequently depths, were varied to observe different delamination features over the penetration depth at the substrate-coating interface. Additionally, the scratches were observed in-situ with scanning electron microscopy (SEM) to better understand the changes in lateral force during the test. The results showed that cohesive failure in AF4 happens before adhesive failure at indentation depths down to $1,4 mumathrm{m}$, At $1,4 mumathrm{m}$ depth we can observe first adhesive failure features on the AF4 coating - SiO2 substrate interface. This shows that the AF4 coating on the SiO2 substrate has a slightly lower adhesion than on the Si substrate. The adhesion failures on both samples start to occur at scratches near the AF4-substrate interface, without chipping on the sides. The results also showed that if the scratch depth is not near the AF4-substrate, only the cohesive failure in AF4 can be seen, which indicates very good adhesion for both samples.","PeriodicalId":163034,"journal":{"name":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126304742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-07DOI: 10.1109/EPTC56328.2022.10013086
Xiaoming Wang, Haojie Chen, Yang Yang, Lin Cao, Yufeng Jin
Multilayer microstrip interdigital filter has become a research hotspot with the development of miniaturization and high integration. Many electromagnetic optimization methods have been developed with the increasing complexity and design difficulty of multilayer interdigital filters. Aggressive Space Mapping (ASM) algorithm has poor convergence and Implicit Spatial Mapping algorithm is limited to modeling structures with equivalent circuit models in ADS. Hence the improved Trust Region Aggressive Space Mapping (TRASM) algorithm is adopted to map between the coarse and fine models in this paper, where the coarse model is the coupling matrix and the fine model is the model in HFSS. Modal Vector Fitting (MVF) algorithm is used to get the coupling matrix, which enhances the uniqueness of the extraction step. This paper proposes a four-order and four-layer interdigital filter with a pass band of 8–9 GHz and an in-band return loss of 20.34 dB. The TRASM method based on MVF can complete the optimization in about 90 minutes with only two iterations, which is better than that of ASM and full- wave electromagnetic simulation. The innovative algorithm with efficient optimization proposed in this paper will be applied in electromagnetic optimization of multilayer filters extensively and improve the accuracy and simulation efficiency significantly.
随着微型化和高集成化的发展，多层微带数字间滤波器已成为研究热点。随着多层数字间滤波器的复杂性和设计难度的增加，人们开发了许多电磁优化方法。ASM (Aggressive Space Mapping)算法收敛性差，且隐式空间映射算法在ADS中仅限于用等效电路模型对结构进行建模，因此本文采用改进的Trust Region Aggressive Space Mapping (TRASM)算法在粗模型和精模型之间进行映射，其中粗模型为耦合矩阵，精模型为HFSS中的模型。采用模态向量拟合(Modal Vector Fitting, MVF)算法得到耦合矩阵，增强了提取步骤的唯一性。本文提出了一种四阶四层数字间滤波器，其通频带为8 - 9ghz，带内回波损耗为20.34 dB。基于MVF的TRASM方法只需两次迭代即可在90分钟左右完成优化，优于ASM和全波电磁仿真。本文提出的高效优化的创新算法将广泛应用于多层滤波器的电磁优化，显著提高精度和仿真效率。
{"title":"Fast Design of a Multilayer Interdigital Filter Exploiting Trust Region Aggressive Space Mapping","authors":"Xiaoming Wang, Haojie Chen, Yang Yang, Lin Cao, Yufeng Jin","doi":"10.1109/EPTC56328.2022.10013086","DOIUrl":"https://doi.org/10.1109/EPTC56328.2022.10013086","url":null,"abstract":"Multilayer microstrip interdigital filter has become a research hotspot with the development of miniaturization and high integration. Many electromagnetic optimization methods have been developed with the increasing complexity and design difficulty of multilayer interdigital filters. Aggressive Space Mapping (ASM) algorithm has poor convergence and Implicit Spatial Mapping algorithm is limited to modeling structures with equivalent circuit models in ADS. Hence the improved Trust Region Aggressive Space Mapping (TRASM) algorithm is adopted to map between the coarse and fine models in this paper, where the coarse model is the coupling matrix and the fine model is the model in HFSS. Modal Vector Fitting (MVF) algorithm is used to get the coupling matrix, which enhances the uniqueness of the extraction step. This paper proposes a four-order and four-layer interdigital filter with a pass band of 8–9 GHz and an in-band return loss of 20.34 dB. The TRASM method based on MVF can complete the optimization in about 90 minutes with only two iterations, which is better than that of ASM and full- wave electromagnetic simulation. The innovative algorithm with efficient optimization proposed in this paper will be applied in electromagnetic optimization of multilayer filters extensively and improve the accuracy and simulation efficiency significantly.","PeriodicalId":163034,"journal":{"name":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127951118","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-07DOI: 10.1109/EPTC56328.2022.10013194
H. Bao, Tianhan Liu, Minjie Ning, Weiping Du, Yufeng Liu, Zongbei Dai
Micro-bumps are one kind of the CoWoS package structures. Finite element analysis (FEA) simulation was used to more accurately investigate micro-bumps mechanical behaviour (e.g. stress-strain state, lifetime prediction) at different cyclic thermal loading rates (mimic the thermal cycling and thermal shock in JEDEC JESD22 A106B/A104E conditions). Considering the difference in thermal expansion coefficients of each material in the CoWoS structure, the material properties of each structure were fed into the simulation. The results showed that the cyclic thermal loading rate influences the maximum equivalent strain, which is larger at slower thermal loading rates. However, the maximum equivalent stress and the maximum strain energy density are larger at faster thermal loads. In addition, the regions with the maximum equivalent stress and the maximum strain energy density normally are located closed to the most distal part of the micro-bumps. Finally, this paper also presents a lifetime prediction for micro-bumps by Engelmaier model, which could be a reference only. The lifetime prediction indicated that faster thermal loading rates lead to micro-bumps greater stress-strain concentration, which in turn reduce lifetime.
{"title":"The effect of cyclic thermal loading rate on the mechanical behavior of micro-bumps in CoWoS package","authors":"H. Bao, Tianhan Liu, Minjie Ning, Weiping Du, Yufeng Liu, Zongbei Dai","doi":"10.1109/EPTC56328.2022.10013194","DOIUrl":"https://doi.org/10.1109/EPTC56328.2022.10013194","url":null,"abstract":"Micro-bumps are one kind of the CoWoS package structures. Finite element analysis (FEA) simulation was used to more accurately investigate micro-bumps mechanical behaviour (e.g. stress-strain state, lifetime prediction) at different cyclic thermal loading rates (mimic the thermal cycling and thermal shock in JEDEC JESD22 A106B/A104E conditions). Considering the difference in thermal expansion coefficients of each material in the CoWoS structure, the material properties of each structure were fed into the simulation. The results showed that the cyclic thermal loading rate influences the maximum equivalent strain, which is larger at slower thermal loading rates. However, the maximum equivalent stress and the maximum strain energy density are larger at faster thermal loads. In addition, the regions with the maximum equivalent stress and the maximum strain energy density normally are located closed to the most distal part of the micro-bumps. Finally, this paper also presents a lifetime prediction for micro-bumps by Engelmaier model, which could be a reference only. The lifetime prediction indicated that faster thermal loading rates lead to micro-bumps greater stress-strain concentration, which in turn reduce lifetime.","PeriodicalId":163034,"journal":{"name":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121634242","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：