Cycle-domain simulator for phase-locked loops

Abstract

As computers become faster and more complex, clock synthesis becomes critical. Due to the relatively slower bus clocks compared to the processor, it is necessary to use phase-locked loops (PLL) for multiplication and phase aligning of the clocks. A PLL is composed of both digital and analog components and is not modeled well in a design environment for digital systems. There are design tools available that are more adept for doing PLL simulations; however, they can be very costly and are still not suitable for the way PLL's are used in computer systems. The goal of this paper is to introduce a new simulator that is specifically designed for simulating PLL's used in computer systems.