Pub Date : 2000-02-27DOI: 10.1109/SSMSD.2000.836454
G. Palumbo, S. Pennisi
The nested Miller compensation of three-stage amplifiers is reviewed by using a novel and simple design-oriented approach allowing the control of the overall phase margin as well as that of each internal loop. Furthermore, a novel technique using nulling resistors to remove the RHP zeroes is discussed which greatly improves frequency and slew-rate performance, without increasing the power consumption. Thanks to the small compensation capacitors employed, the approach is suited for integration and in particular where large load capacitors have to be driven. SPICE simulations based on a 0.8-/spl mu/m CMOS design are given and found in remarkable agreement with the theoretical analysis.
{"title":"Design guidelines for optimized nested Miller compensation","authors":"G. Palumbo, S. Pennisi","doi":"10.1109/SSMSD.2000.836454","DOIUrl":"https://doi.org/10.1109/SSMSD.2000.836454","url":null,"abstract":"The nested Miller compensation of three-stage amplifiers is reviewed by using a novel and simple design-oriented approach allowing the control of the overall phase margin as well as that of each internal loop. Furthermore, a novel technique using nulling resistors to remove the RHP zeroes is discussed which greatly improves frequency and slew-rate performance, without increasing the power consumption. Thanks to the small compensation capacitors employed, the approach is suited for integration and in particular where large load capacitors have to be driven. SPICE simulations based on a 0.8-/spl mu/m CMOS design are given and found in remarkable agreement with the theoretical analysis.","PeriodicalId":166604,"journal":{"name":"2000 Southwest Symposium on Mixed-Signal Design (Cat. No.00EX390)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-02-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123125514","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-02-27DOI: 10.1109/SSMSD.2000.836455
W. Sheng, E. Sánchez-Sinencio
Mobile communications systems will evolve towards a third generation at the beginning of the new millenium. Third generation is built on the backward compatibility with the second generation networks. Thus wideband multi-standard receivers, which are able to operate according to multiple mobile communication standards, will be required by the third generation system users. This paper presents a number of system issues and design considerations which are involved in the design of wideband multi-standard DCS1800/UMTS digital receiver, and in particular the analog-to-digital converter (ADC) technology requirements for the implementation is presented.
{"title":"System design considerations of wideband multi-standard receiver for 3rd generation mobile system applications","authors":"W. Sheng, E. Sánchez-Sinencio","doi":"10.1109/SSMSD.2000.836455","DOIUrl":"https://doi.org/10.1109/SSMSD.2000.836455","url":null,"abstract":"Mobile communications systems will evolve towards a third generation at the beginning of the new millenium. Third generation is built on the backward compatibility with the second generation networks. Thus wideband multi-standard receivers, which are able to operate according to multiple mobile communication standards, will be required by the third generation system users. This paper presents a number of system issues and design considerations which are involved in the design of wideband multi-standard DCS1800/UMTS digital receiver, and in particular the analog-to-digital converter (ADC) technology requirements for the implementation is presented.","PeriodicalId":166604,"journal":{"name":"2000 Southwest Symposium on Mixed-Signal Design (Cat. No.00EX390)","volume":"806 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-02-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116418870","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-02-27DOI: 10.1109/SSMSD.2000.836450
N. James
As computers become faster and more complex, clock synthesis becomes critical. Due to the relatively slower bus clocks compared to the processor, it is necessary to use phase-locked loops (PLL) for multiplication and phase aligning of the clocks. A PLL is composed of both digital and analog components and is not modeled well in a design environment for digital systems. There are design tools available that are more adept for doing PLL simulations; however, they can be very costly and are still not suitable for the way PLL's are used in computer systems. The goal of this paper is to introduce a new simulator that is specifically designed for simulating PLL's used in computer systems.
{"title":"Cycle-domain simulator for phase-locked loops","authors":"N. James","doi":"10.1109/SSMSD.2000.836450","DOIUrl":"https://doi.org/10.1109/SSMSD.2000.836450","url":null,"abstract":"As computers become faster and more complex, clock synthesis becomes critical. Due to the relatively slower bus clocks compared to the processor, it is necessary to use phase-locked loops (PLL) for multiplication and phase aligning of the clocks. A PLL is composed of both digital and analog components and is not modeled well in a design environment for digital systems. There are design tools available that are more adept for doing PLL simulations; however, they can be very costly and are still not suitable for the way PLL's are used in computer systems. The goal of this paper is to introduce a new simulator that is specifically designed for simulating PLL's used in computer systems.","PeriodicalId":166604,"journal":{"name":"2000 Southwest Symposium on Mixed-Signal Design (Cat. No.00EX390)","volume":"14 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-02-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114618902","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-02-27DOI: 10.1109/SSMSD.2000.836436
S. Levitan, J.A. Martinez, T. Kurzweg, M. T. Shomsky, P. Marchand, D. Chiarulli
Chatoyant is a system level opto-electro-mechanical CAD tool developed to meet the needs of mixed technology systems designers. In this paper, we present the modeling techniques we have implemented in Chatoyant for system level design of mixed technology micro-systems composed of optical, electrical and mechanical components.
{"title":"Modeling and simulation of mixed technology micro systems","authors":"S. Levitan, J.A. Martinez, T. Kurzweg, M. T. Shomsky, P. Marchand, D. Chiarulli","doi":"10.1109/SSMSD.2000.836436","DOIUrl":"https://doi.org/10.1109/SSMSD.2000.836436","url":null,"abstract":"Chatoyant is a system level opto-electro-mechanical CAD tool developed to meet the needs of mixed technology systems designers. In this paper, we present the modeling techniques we have implemented in Chatoyant for system level design of mixed technology micro-systems composed of optical, electrical and mechanical components.","PeriodicalId":166604,"journal":{"name":"2000 Southwest Symposium on Mixed-Signal Design (Cat. No.00EX390)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-02-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125706712","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-02-27DOI: 10.1109/SSMSD.2000.836437
A. Krishnamoorthy
The concept of a manufacturable technology that can provide parallel optical interconnects directly to a VLSI circuit now appears to be a reality. One such optoelectronic-VLSI (OE-VLSI) technology is based on the hybrid flip-chip area bonding of GaAs/AlGaAs multiple-quantum well (MQW) electro-absorption modulator devices directly onto active silicon CMOS circuits. The technology has reached the point where batchfabricated foundry shuttle incorporating multiple OE-VLSI chip designs are now being run. These foundry shuttles represent the first delivery of custom-designed CMOS VLSI chips with surface-normal optical I/O technology. From a systems point of view, this represents an important step towards the entry of optical interconnects in that: the silicon integrated circuit is state-of-the-art; the circuit is unaffected by the integration process; and the architecture, design, and optimization of the chip can proceed independently of the placement and bonding to the optical I/O.
{"title":"Terabit/s optical I/O directly to VLSI chips","authors":"A. Krishnamoorthy","doi":"10.1109/SSMSD.2000.836437","DOIUrl":"https://doi.org/10.1109/SSMSD.2000.836437","url":null,"abstract":"The concept of a manufacturable technology that can provide parallel optical interconnects directly to a VLSI circuit now appears to be a reality. One such optoelectronic-VLSI (OE-VLSI) technology is based on the hybrid flip-chip area bonding of GaAs/AlGaAs multiple-quantum well (MQW) electro-absorption modulator devices directly onto active silicon CMOS circuits. The technology has reached the point where batchfabricated foundry shuttle incorporating multiple OE-VLSI chip designs are now being run. These foundry shuttles represent the first delivery of custom-designed CMOS VLSI chips with surface-normal optical I/O technology. From a systems point of view, this represents an important step towards the entry of optical interconnects in that: the silicon integrated circuit is state-of-the-art; the circuit is unaffected by the integration process; and the architecture, design, and optimization of the chip can proceed independently of the placement and bonding to the optical I/O.","PeriodicalId":166604,"journal":{"name":"2000 Southwest Symposium on Mixed-Signal Design (Cat. No.00EX390)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-02-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133040884","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-02-27DOI: 10.1109/SSMSD.2000.836447
J. Wikner, M. Vesterbacka
In design of high-speed, high resolution D/A converters, glitches in the output are of major concern. To tradeoff between hardware complexity and glitch performance the current practice is to use a hybrid converter where the most significant bits are thermometer coded and the least significant bits are binary-scaled. As an alternative to this scheme, we propose a new method for D/A conversion based on linear coding of the weights (1, 2, 3,...). The new method improves the glitch performance and reduces the hardware complexity for high resolution converters. An algorithm for converting the digital binary-coded input word into a digital word controlling the linear weights is given. In an example, the linear-coded weights are applied to a current-steering D/A converter. We discuss properties such as layout properties, device matching, and mixed-signal issues.
{"title":"D/A conversion with linear-coded weights","authors":"J. Wikner, M. Vesterbacka","doi":"10.1109/SSMSD.2000.836447","DOIUrl":"https://doi.org/10.1109/SSMSD.2000.836447","url":null,"abstract":"In design of high-speed, high resolution D/A converters, glitches in the output are of major concern. To tradeoff between hardware complexity and glitch performance the current practice is to use a hybrid converter where the most significant bits are thermometer coded and the least significant bits are binary-scaled. As an alternative to this scheme, we propose a new method for D/A conversion based on linear coding of the weights (1, 2, 3,...). The new method improves the glitch performance and reduces the hardware complexity for high resolution converters. An algorithm for converting the digital binary-coded input word into a digital word controlling the linear weights is given. In an example, the linear-coded weights are applied to a current-steering D/A converter. We discuss properties such as layout properties, device matching, and mixed-signal issues.","PeriodicalId":166604,"journal":{"name":"2000 Southwest Symposium on Mixed-Signal Design (Cat. No.00EX390)","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-02-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116374013","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-02-27DOI: 10.1109/SSMSD.2000.836465
M. Michael, S. Tragoudas
A novel methodology for non-enumerative ATPG for path delay faults is presented. Tests are generated by manipulating, in a systematic yet simple way, sets of pairs of functions. Each pair of functions represents the constraints to be satisfied by the non-enumerative delay fault test for each time frame of a transition. A test that detects many faults is generated from each pair of functions. A current ROBDD-based implementation of this technique is used to analyze the delay fault testability of the ISCAS'85 benchmark circuits.
{"title":"Functional-based ATPG for path delay faults","authors":"M. Michael, S. Tragoudas","doi":"10.1109/SSMSD.2000.836465","DOIUrl":"https://doi.org/10.1109/SSMSD.2000.836465","url":null,"abstract":"A novel methodology for non-enumerative ATPG for path delay faults is presented. Tests are generated by manipulating, in a systematic yet simple way, sets of pairs of functions. Each pair of functions represents the constraints to be satisfied by the non-enumerative delay fault test for each time frame of a transition. A test that detects many faults is generated from each pair of functions. A current ROBDD-based implementation of this technique is used to analyze the delay fault testability of the ISCAS'85 benchmark circuits.","PeriodicalId":166604,"journal":{"name":"2000 Southwest Symposium on Mixed-Signal Design (Cat. No.00EX390)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-02-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126447605","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-02-27DOI: 10.1109/SSMSD.2000.836452
B. Atwood, B. Warneke, K. Pister
In this paper we present a miniature system that is being designed for the Smart Dust project to test the communication link and simulate basic functionality. The system includes an optical receiver to process the incoming laser signal, digital circuits to generate a pseudorandom number sequence, a corner cube reflector (CCR) to passively transmit data to the base station, and a charge pump to generate the voltages required for the CCR. The circuits are being fabricated in a 0.25 /spl mu/m twin-well 5 metal layer CMOS process and the CCR has been fabricated in the MCNC MUMPS 3 structural polysilicon layer (MEMS) process. The components are to be mounted onto a 1.4 V zinc-air hearing aid style battery and the entire system can fit into a 5.8 mm/spl times/5.8 mm/spl times/2.4 mm package.
{"title":"Preliminary circuits for Smart Dust","authors":"B. Atwood, B. Warneke, K. Pister","doi":"10.1109/SSMSD.2000.836452","DOIUrl":"https://doi.org/10.1109/SSMSD.2000.836452","url":null,"abstract":"In this paper we present a miniature system that is being designed for the Smart Dust project to test the communication link and simulate basic functionality. The system includes an optical receiver to process the incoming laser signal, digital circuits to generate a pseudorandom number sequence, a corner cube reflector (CCR) to passively transmit data to the base station, and a charge pump to generate the voltages required for the CCR. The circuits are being fabricated in a 0.25 /spl mu/m twin-well 5 metal layer CMOS process and the CCR has been fabricated in the MCNC MUMPS 3 structural polysilicon layer (MEMS) process. The components are to be mounted onto a 1.4 V zinc-air hearing aid style battery and the entire system can fit into a 5.8 mm/spl times/5.8 mm/spl times/2.4 mm package.","PeriodicalId":166604,"journal":{"name":"2000 Southwest Symposium on Mixed-Signal Design (Cat. No.00EX390)","volume":"159 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-02-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115274235","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-02-27DOI: 10.1109/SSMSD.2000.836445
N. Andersson, J. Wikner
Interesting comparisons of dynamic element matching (DEM) techniques, have been presented during the last decade. However, not many chip implementations of these DEM techniques have been presented so far. A brief review of different DEM techniques are presented in this paper together with a strategy for implementing the partial randomization DEM, PRDEM, technique in a 3.3 V supply, 14 bit CMOS current-steering wideband digital-to-analog converter (DAC).
{"title":"A strategy for implementing dynamic element matching in current-steering DACs","authors":"N. Andersson, J. Wikner","doi":"10.1109/SSMSD.2000.836445","DOIUrl":"https://doi.org/10.1109/SSMSD.2000.836445","url":null,"abstract":"Interesting comparisons of dynamic element matching (DEM) techniques, have been presented during the last decade. However, not many chip implementations of these DEM techniques have been presented so far. A brief review of different DEM techniques are presented in this paper together with a strategy for implementing the partial randomization DEM, PRDEM, technique in a 3.3 V supply, 14 bit CMOS current-steering wideband digital-to-analog converter (DAC).","PeriodicalId":166604,"journal":{"name":"2000 Southwest Symposium on Mixed-Signal Design (Cat. No.00EX390)","volume":"117 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-02-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116022965","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-02-27DOI: 10.1109/SSMSD.2000.836444
Shenggao Li, J. Zohios, JungBum Choi, M. Ismail
This paper presents the design of a Gilbert downconversion mixer for wideband CDMA application. The mixer is designed using a 0.18 /spl mu/m 1.5 V/3.3 V dual voltage digital CMOS technology. The design methodology is presented to achieve high linearity and low noise figure. A design flow is introduced targeting the automatic design and optimization for mixers.
{"title":"RF CMOS mixer design and optimization for wideband CDMA application","authors":"Shenggao Li, J. Zohios, JungBum Choi, M. Ismail","doi":"10.1109/SSMSD.2000.836444","DOIUrl":"https://doi.org/10.1109/SSMSD.2000.836444","url":null,"abstract":"This paper presents the design of a Gilbert downconversion mixer for wideband CDMA application. The mixer is designed using a 0.18 /spl mu/m 1.5 V/3.3 V dual voltage digital CMOS technology. The design methodology is presented to achieve high linearity and low noise figure. A design flow is introduced targeting the automatic design and optimization for mixers.","PeriodicalId":166604,"journal":{"name":"2000 Southwest Symposium on Mixed-Signal Design (Cat. No.00EX390)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-02-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116119210","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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