H. Schmit, David Whelihan, Andrew Tsai, M. Moe, B. Levine, R. Taylor
{"title":"PipeRench: A virtualized programmable datapath in 0.18 micron technology","authors":"H. Schmit, David Whelihan, Andrew Tsai, M. Moe, B. Levine, R. Taylor","doi":"10.1109/CICC.2002.1012767","DOIUrl":null,"url":null,"abstract":"PipeRench is a programmable datapath that can be used to accelerate numerically intensive applications. The unique aspect of PipeRench is its ability to virtualize hardware through self-managed dynamic reconfiguration. This capability provides application portability and scalability without redesign or recompilation. This paper describes the implementation of PipeRench in a 0.18 micron process. The implementation has 3.65 million transistors and runs at 120 MHz. Performance is competitive with high-end commercial DSP architectures and more than five times faster than a commercial microprocessor. Executing at 33 MHz, an FIR filter without virtualization consumes 519 mW. When virtualization is required, the implementation consumes approximately 675 mW.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"169","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.2002.1012767","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 169
Abstract
PipeRench is a programmable datapath that can be used to accelerate numerically intensive applications. The unique aspect of PipeRench is its ability to virtualize hardware through self-managed dynamic reconfiguration. This capability provides application portability and scalability without redesign or recompilation. This paper describes the implementation of PipeRench in a 0.18 micron process. The implementation has 3.65 million transistors and runs at 120 MHz. Performance is competitive with high-end commercial DSP architectures and more than five times faster than a commercial microprocessor. Executing at 33 MHz, an FIR filter without virtualization consumes 519 mW. When virtualization is required, the implementation consumes approximately 675 mW.