A communication structure to implement a multi-microprocessor computer architecture

Abstract

From the results of research dealing with the overall system architecture of a nodal processor system, a major problem was the way in which nodes (individual) processors can effectively communicate with each other. This paper presents a proposed communications method for a set of interconnected micro-processors. The proposed communication system provides for a multitude of communication buses and the ability for simultaneous direct communication between all microcomputers connected to the same communication bus, which would be a single wire. Also any microcomputer within this structure can select to communicate over three different orthogonally arranged buses. To make this possible a special transmitter receiver circuit must be associated with each microcomputer. Although only one physical wire makes up an individual communication path, simultaneous direct communication is possible among any combination of microcomputers connected to a bus by phase modulation of individually selected binary orthogonal waveforms (Walsh Functions) generated by the special communications circuit. The information is separated in sequency [@@@@] instead of in space. Each microcomputer must be programmed with the information as to what sequencys of Walsh Functions are to be used to transmit or receive information at specific times. The general geometric arrangement for this communication structure would be somewhat similar to that of a three-wire three-dimensional core memory, where in this case microcomputers and their associated memorys would be located geometrically analogous to where the cores are located in a core memory. Such a computer structure is completely homogenous thus offering high reliability and also provides the capability for a high degree of parallelism when computing.