PVT-variation based Comparative Analysis of Write Driver Designs for SRAM at 32 nm

Abstract

In this paper, the existing write driver designs for SRAM are analyzed at 32 nm technology node. The performance of the designs are compared on the basis of Write Delay, Write Power consumption, Energy per Switching activity and Complexity of the design. The simulations are also done under PVT-variations to observe the impact of different operating conditions on the performance of the design. From the results, it is observed that the NOR gate based design performs fastest write operation with up to 9 % improvement in Write Delay. The Pass gate based design consumes least Write Power and Energy per Switching activity with up to 55.9 % and 51.5 % reduction respectively at TT corner, 1.1 V, 27 °C. In addition, the results show that the Write Delay of all the designs suffer at SF corner, low supply voltage and low temperatures. Alternatively, the designs perform faster write operation at FS corner, high supply voltages and high temperatures. The Write Power consumption is minimum at SS corner, low supply voltages and high temperatures and maximum at FF corner, high supply voltages and high temperatures. The Energy consumed per Switching activity is least at SS corner, low supply voltages and high temperatures.