An efficient test generation technique for sequential circuits with repetitive sub-circuits

Proceedings of 9th International Conference on VLSI Design Pub Date : 1996-01-03 DOI:10.1109/ICVD.1996.489480

Dhruva R. Chakrabarti, Ajai Jain

引用次数: 2

Abstract

An efficient hierarchical testing algorithm for sequential circuits with repetitive sub-circuits has been proposed and implemented. This algorithm uses the bus fault model which helps in significant reduction of modeled circuit components and faults. The algorithm is significantly faster than conventional gate-level test generators for a class of sequential circuits since it attempts to generate test vectors in parallel. The algorithm resolves high-level incompatibility encountered during test generation whenever it is possible. This is done by unfolding the high-level model of the circuit and obtaining a loop in the corresponding state transition graph.

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具有重复子电路的顺序电路的有效测试生成技术

提出并实现了一种具有重复子电路的顺序电路的有效分层测试算法。该算法采用总线故障模型，有助于显著减少建模电路元件和故障。对于一类顺序电路，该算法比传统的门级测试生成器要快得多，因为它试图并行地生成测试向量。只要有可能，该算法可以解决在测试生成过程中遇到的高级不兼容性问题。这是通过展开电路的高级模型并在相应的状态转换图中获得环路来完成的。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Proceedings of 9th International Conference on VLSI Design

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