Design of low-power acceleration processor for convolutional neural networks based on RISC-V

Abstract

A low-power RISC-V-based convolutional neural network acceleration processor is proposed to cope with the problem that the increasing resource requirements of convolutional neural networks in the direction of hardware convolutional acceleration are difficult to be met on embedded devices. The processor is designed with three instructions that can configure the parameters of each CNN layer to accommodate different input data, multiplex computational resources to reduce power consumption, and execute operations that repeat a large number of executions in parallel to speed up operation efficiency. Through comparison experiments, it can be found that this processor acceleration instruction set is 20.93 times, 7.67 times, and 8.97 times faster than the base RISC-V instruction set after verified with the same data on three operations, including convolution, activation, and pooling, respectively. The experimental results show that the total power consumption of the processor with this custom instruction set is only 0.221 W at 16 MHZ operating frequency, which is advantageous in terms of performance-to-power ratio compared to other RISC-V accelerated processors with less resource consumption and lower power consumption.