Lightweight Hardware Architectures for the Piccolo Block Cipher in FPGA

Abstract

The Piccolo block cipher is a lightweight block encryption for hardware use. Hardware devices are equipped with limited computation resources and small memory. In this paper, we propose an implementation to carry out through several trade-offs between area and speed. We implemented the Piccolo block cipher algorithm with 128-bit key in two different architectures on FPGA: the iterative and the 4-bit serial architectures. The proposed implementation was performed on Xilinx Spartan-3. The iterative implementation achieves 76% of resource utilization. This implementation takes 31 clock cycles to perform the encryption or decryption. So, it results in a throughput of 151.1 Mbps. The serial implementation was optimized in terms of area to reduce the cost. It achieves 54% of resource utilization and takes 496 clock cycles resulting in a throughput of 6.39 Mbps.