Hardware architecture dedicated for arithmetic mean filtration implemented in FPGA

Abstract

An FPGA-based hardware architecture for arithmetic mean filtration optimized with 49-pixel square neighborhood is proposed. The arithmetic mean formula is optimized and transformed into the new formula that introduces the computational cyclic sequence which results in multiplication-less process with only 9 additions necessary for each pixel. The external memory is used to save partial results but the memory requirement has been optimized so the requirement is the same as for the input data. This proposed architecture is oriented to security tracking applications; however, it can be used in any image processing applications that use arithmetic mean filtering. It is resolution and frame rate independent and suitable for all high resolution and multiple camera systems. FPGA optimization made it also suitable for FPGA-based reconfigurable systems and computing.