Thermal effect aware X-bit filling technique for peak temperature reduction during VLSI testing

Abstract

Power density for digital circuits is increasing by leaps and bounds with the progress of technology and increased integration. Higher spatial power density contemplates heat generation which raises peak temperature affecting flawless system behavior. The situation is worsened further during testing and this rise in temperature during test can permanently spoil the chip. To resolve this problem, significant efforts are rendered by the academia and industry for controlling temperature rise during test mode operation and peak temperature reduction is viewed as a sub problem in this context. Controlling of temperature divergence is also needed to bring temperature distribution homogeneity across the chip. Heat generated inside a chip under test can be dropped down by lowering inter test cube switching activity. Controlling of peak temperature and temperature divergence with in a safe legitimate threshold may be accomplished by an intelligent don't care bit filling approach which especially takes care of thermal effect and drops down switching activity inside a circuit block. In this paper, a thermal effect aware don't care (X) filling approach is put forwarded which controls peak temperature and temperature divergence within a predefined threshold during testing. This proposal is verified by extensive simulation on ITC'99 benchmark circuits and exhibits a satisfactory level of efficacy.