An Efficient Segmented Random Access Scan Architecture with Test Compression

M. Karunaratne, B. Oomman
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Abstract

Integrated circuit (IC) chip designs relying on Random Access Scan (RAS) architecture for post-production structural tests typically provide lower test power dissipation, test data volume, and test application time compared to the classical serial scan-based Design for Test (DFT) methodology. However, previous RAS schemes incur high signal routing and test area overheads relative to the serial scan way. Unlike serial scan schemes, previous RAS schemes have not been effectively combined with test compression to further reduce test application time and test data volume. Authors have already formally documented a locally addressed (segmented) and compressed Segmented RAS (SRAS) architecture with low area overhead and test application time. This paper describes the SRAS architecture in more detail and provides comparative experimental results. Area overhead is reduced using test access hierarchy (segmented), while adding compression to RAS lowers the test application time. Also presented is another enhancement to incorporate a scan channel multiplex block at hierarchy segments which helps drastically decrease the area and routing overhead of the original architecture to practically implementable levels on commercial circuits. The extra Segment Data Multiplexor (SDM) blocks reduce the area overhead of other components by the multiplexing factor, and the reduction in overall area is significant based on experimental data. Test data compression and auto addressing of segments are achieved by transmitting a seed address to select segments with auto-increment or auto-decrement capability followed by either single cell selection or entire leaf cell segment selection. To further reduce the area overhead and test power, this architecture is enhanced to contain multiple channels at a cost of increased overall test application time with no increase in test data volume. Results of applying the enhancements to a large circuit with one level of intermediate segments with each of them having 256 leaf segments are presented in the paper with and without multichannel multiplexing for comparison.
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一种具有测试压缩的高效分段随机访问扫描结构
与传统的基于串行扫描的测试设计(DFT)方法相比,依靠随机存取扫描(RAS)架构进行后期结构测试的集成电路(IC)芯片设计通常提供更低的测试功耗、测试数据量和测试应用时间。然而,先前的RAS方案相对于串行扫描方式会产生较高的信号路由和测试面积开销。与串行扫描方案不同,以前的RAS方案没有有效地与测试压缩相结合,以进一步减少测试应用时间和测试数据量。作者已经正式记录了本地寻址(分段)和压缩分段RAS (SRAS)架构,具有低区域开销和测试应用时间。本文详细介绍了SRAS的结构,并给出了对比实验结果。使用测试访问层次结构(分段)减少了区域开销,同时向RAS添加压缩降低了测试应用程序时间。此外,还提出了另一种改进,即在分层段中加入扫描通道多路复用块,这有助于将原始架构的面积和路由开销大大减少到商业电路上实际可实现的水平。额外的分段数据复用(SDM)块通过复用因子减少了其他组件的面积开销,从实验数据来看,总体面积的减少是显著的。测试数据压缩和段的自动寻址是通过传输种子地址来选择具有自动递增或自动递减能力的段,然后进行单细胞选择或整个叶细胞段选择来实现的。为了进一步减少面积开销和测试功率,该体系结构被增强为包含多个通道,其代价是增加了总体测试应用程序时间,而不增加测试数据量。将增强应用于具有一级中间段的大型电路,其中每个中间段具有256个叶段,本文给出了使用和不使用多路复用的结果进行比较。
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