Pub Date : 2023-04-29DOI: 10.5121/vlsic.2023.14202
M. Karunaratne, B. Oomman
Integrated circuit (IC) chip designs relying on Random Access Scan (RAS) architecture for post-production structural tests typically provide lower test power dissipation, test data volume, and test application time compared to the classical serial scan-based Design for Test (DFT) methodology. However, previous RAS schemes incur high signal routing and test area overheads relative to the serial scan way. Unlike serial scan schemes, previous RAS schemes have not been effectively combined with test compression to further reduce test application time and test data volume. Authors have already formally documented a locally addressed (segmented) and compressed Segmented RAS (SRAS) architecture with low area overhead and test application time. This paper describes the SRAS architecture in more detail and provides comparative experimental results. Area overhead is reduced using test access hierarchy (segmented), while adding compression to RAS lowers the test application time. Also presented is another enhancement to incorporate a scan channel multiplex block at hierarchy segments which helps drastically decrease the area and routing overhead of the original architecture to practically implementable levels on commercial circuits. The extra Segment Data Multiplexor (SDM) blocks reduce the area overhead of other components by the multiplexing factor, and the reduction in overall area is significant based on experimental data. Test data compression and auto addressing of segments are achieved by transmitting a seed address to select segments with auto-increment or auto-decrement capability followed by either single cell selection or entire leaf cell segment selection. To further reduce the area overhead and test power, this architecture is enhanced to contain multiple channels at a cost of increased overall test application time with no increase in test data volume. Results of applying the enhancements to a large circuit with one level of intermediate segments with each of them having 256 leaf segments are presented in the paper with and without multichannel multiplexing for comparison.
{"title":"An Efficient Segmented Random Access Scan Architecture with Test Compression","authors":"M. Karunaratne, B. Oomman","doi":"10.5121/vlsic.2023.14202","DOIUrl":"https://doi.org/10.5121/vlsic.2023.14202","url":null,"abstract":"Integrated circuit (IC) chip designs relying on Random Access Scan (RAS) architecture for post-production structural tests typically provide lower test power dissipation, test data volume, and test application time compared to the classical serial scan-based Design for Test (DFT) methodology. However, previous RAS schemes incur high signal routing and test area overheads relative to the serial scan way. Unlike serial scan schemes, previous RAS schemes have not been effectively combined with test compression to further reduce test application time and test data volume. Authors have already formally documented a locally addressed (segmented) and compressed Segmented RAS (SRAS) architecture with low area overhead and test application time. This paper describes the SRAS architecture in more detail and provides comparative experimental results. Area overhead is reduced using test access hierarchy (segmented), while adding compression to RAS lowers the test application time. Also presented is another enhancement to incorporate a scan channel multiplex block at hierarchy segments which helps drastically decrease the area and routing overhead of the original architecture to practically implementable levels on commercial circuits. The extra Segment Data Multiplexor (SDM) blocks reduce the area overhead of other components by the multiplexing factor, and the reduction in overall area is significant based on experimental data. Test data compression and auto addressing of segments are achieved by transmitting a seed address to select segments with auto-increment or auto-decrement capability followed by either single cell selection or entire leaf cell segment selection. To further reduce the area overhead and test power, this architecture is enhanced to contain multiple channels at a cost of increased overall test application time with no increase in test data volume. Results of applying the enhancements to a large circuit with one level of intermediate segments with each of them having 256 leaf segments are presented in the paper with and without multichannel multiplexing for comparison.","PeriodicalId":263158,"journal":{"name":"International Journal of VLSI Design & Communication Systems","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114716628","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-04-29DOI: 10.5121/vlsic.2023.14201
M. U. Shariff, Vineeth Kumar Veepuri, Nancy Dimri, Mahadevaswamy B N
This paper explores the use of macros and parameters in Hardware Description Language (HDL) programming. Macros and parameters are powerful tools that allow for efficient and reusable code, yet their full potential is often underutilized. By examining the advantages of macros and parameters, this paper aims to demonstrate how these features can enhance the flexibility, readability, and maintainability of HDL code. Additionally, the paper discusses the use cases of mixing macros and parameters in HDL programming, highlighting their applicability in a range of scenarios. Furthermore, the paper addresses the challenges that arise from the mix use of macros and parameters and provides best practices to overcome these challenges. Overall, this paper aims to encourage HDL programmers to fully explore the capabilities of macros and parameters in their code, leading to more efficient and effective hardware designs and verification.
{"title":"Mighty Macros and Powerful Parameters: Maximizing Efficiency and Flexibility in HDL Programming","authors":"M. U. Shariff, Vineeth Kumar Veepuri, Nancy Dimri, Mahadevaswamy B N","doi":"10.5121/vlsic.2023.14201","DOIUrl":"https://doi.org/10.5121/vlsic.2023.14201","url":null,"abstract":"This paper explores the use of macros and parameters in Hardware Description Language (HDL) programming. Macros and parameters are powerful tools that allow for efficient and reusable code, yet their full potential is often underutilized. By examining the advantages of macros and parameters, this paper aims to demonstrate how these features can enhance the flexibility, readability, and maintainability of HDL code. Additionally, the paper discusses the use cases of mixing macros and parameters in HDL programming, highlighting their applicability in a range of scenarios. Furthermore, the paper addresses the challenges that arise from the mix use of macros and parameters and provides best practices to overcome these challenges. Overall, this paper aims to encourage HDL programmers to fully explore the capabilities of macros and parameters in their code, leading to more efficient and effective hardware designs and verification.","PeriodicalId":263158,"journal":{"name":"International Journal of VLSI Design & Communication Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129735584","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-30DOI: 10.5121/vlsic.2022.13601
Viraj Joshi, P. Mane, Bits Pilani
When the application context is ready to accept different levels of exactness in solutions and is supported by human perception quality, then the term ‘Approximate Computing’ tossed before one decade will become the first priority . Even though computer hardware and software are working to generate exact results, approximate results are preferred whenever an error is in predefined bound and adaptive. It will reduce power demand and critical path delay and improve other circuit metrics. When it comes to traditional arithmetic circuits, those generating correct results with limitations on performance are rapidly getting replaced by approximate arithmetic circuits which are the need of the hour, and so on about their design.
{"title":"Approximate Arithmetic Circuit Design for Error Resilient Applications","authors":"Viraj Joshi, P. Mane, Bits Pilani","doi":"10.5121/vlsic.2022.13601","DOIUrl":"https://doi.org/10.5121/vlsic.2022.13601","url":null,"abstract":"When the application context is ready to accept different levels of exactness in solutions and is supported by human perception quality, then the term ‘Approximate Computing’ tossed before one decade will become the first priority . Even though computer hardware and software are working to generate exact results, approximate results are preferred whenever an error is in predefined bound and adaptive. It will reduce power demand and critical path delay and improve other circuit metrics. When it comes to traditional arithmetic circuits, those generating correct results with limitations on performance are rapidly getting replaced by approximate arithmetic circuits which are the need of the hour, and so on about their design.","PeriodicalId":263158,"journal":{"name":"International Journal of VLSI Design & Communication Systems","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113959411","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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