XStatic: A Simulation Based ESD Verification and Debug Environment

Abstract

Electrostatic discharge, the transfer of charge between bodies that alters device characteristics has become a major reliability concern in the semiconductor industry. Conventional approaches of using ESD testers to detect ESD defects are post-fabrication methods which leave narrow design time for ESD rectification. This paper discusses a CAD approach which captures ESD problems in the design phase enabling designers to build robust ESD structures. The discussed verification platform performs ESD simulations on the design and aids designers to locate and debug the potential ESD failure nodes in the circuit. This approach leads to robust ESD designs with minimal cycle-time and reduces silicon re-spins.