Pub Date : 2009-05-24DOI: 10.1109/ISCAS.2009.5117674
R. Y. Choi, C. Tsui
This paper proposes a new method for switching the capacitors in the DAC capacitor array of a successive approximation register (SAR) ADC. By separating the decoding of the most significant bits and the least significant bits, and using two different capacitor arrays with unequal size to determine their values, respectively, the average switching energy of the capacitor arrays can be dramatically reduced compared to the conventional switching methods. The analysis of the switching energy reduction is presented. Experiments were carried out on a 10-bit SAR-ADC designed using a 0.35 mum CMOS process. HSPICE simulations show that significant reduction in energy consumption is achieved using the proposed design.
针对逐次逼近寄存器(SAR) ADC的DAC电容阵列，提出了一种切换电容的新方法。通过分离最高有效位和最低有效位的解码，并分别使用两种不同大小的电容阵列来确定其值，与传统的开关方法相比，可以显著降低电容阵列的平均开关能量。对开关能量的降低进行了分析。在采用0.35 μ m CMOS工艺设计的10位SAR-ADC上进行了实验。HSPICE仿真表明，采用该设计可以显著降低能耗。
{"title":"A Low Energy Two-Step Successive Approximation Algorithm for ADC Design","authors":"R. Y. Choi, C. Tsui","doi":"10.1109/ISCAS.2009.5117674","DOIUrl":"https://doi.org/10.1109/ISCAS.2009.5117674","url":null,"abstract":"This paper proposes a new method for switching the capacitors in the DAC capacitor array of a successive approximation register (SAR) ADC. By separating the decoding of the most significant bits and the least significant bits, and using two different capacitor arrays with unequal size to determine their values, respectively, the average switching energy of the capacitor arrays can be dramatically reduced compared to the conventional switching methods. The analysis of the switching energy reduction is presented. Experiments were carried out on a 10-bit SAR-ADC designed using a 0.35 mum CMOS process. HSPICE simulations show that significant reduction in energy consumption is achieved using the proposed design.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116542542","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The effects of random variations during the manufacturing process on devices can be simulated as a variation of transistor parameters. Device degradation, due to temperature or voltage stress, causes a shift of device parameters, for example threshold voltage Vth, which can also be modeled as a degradation of transistor parameters. Therefore, in order to design circuits, which are robust and reliable, analysis and optimization of their sensitivity to variations in model parameters is important. Furthermore, constraints on the operating regions and voltage differences of transistors are used in order to keep operating points stable over a large temperature range. In this work, using two circuits for automotive applications and current process development kits (PDK), we show how design centering software can be used to consider both sensitivity reduction towards model parameter variation and constraints to control safe operating areas (SOA). Beyond that a comparison of the constraint matrix method with two established methods of SOA checking is done.
{"title":"Robust Analog Design for Automotive Applications by Design Centering with Safe Operating Areas","authors":"U. Sobe, Karl-Heinz Rooch, A. Ripp, M. Pronath","doi":"10.1109/ISQED.2008.33","DOIUrl":"https://doi.org/10.1109/ISQED.2008.33","url":null,"abstract":"The effects of random variations during the manufacturing process on devices can be simulated as a variation of transistor parameters. Device degradation, due to temperature or voltage stress, causes a shift of device parameters, for example threshold voltage Vth, which can also be modeled as a degradation of transistor parameters. Therefore, in order to design circuits, which are robust and reliable, analysis and optimization of their sensitivity to variations in model parameters is important. Furthermore, constraints on the operating regions and voltage differences of transistors are used in order to keep operating points stable over a large temperature range. In this work, using two circuits for automotive applications and current process development kits (PDK), we show how design centering software can be used to consider both sensitivity reduction towards model parameter variation and constraints to control safe operating areas (SOA). Beyond that a comparison of the constraint matrix method with two established methods of SOA checking is done.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125093469","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Sundareswaran, J. Abraham, A. Ardelea, R. Panda
With the adoption of statistical timing across industry, there is a need to characterize all gates/cells in a digital library for delay variations (referred to as, statistical characterization). Statistical characterization need to be performed efficiently with acceptable accuracy as a function of several process and environment parameter variations. In this paper, we propose an approach to consider intra-cell process mismatch variations to characterize a cell's delay and output transition time (output slew) variations. A straightforward approach to address this problem is to model these mismatch variations by characterizing for each device fluctuation separately. However, the runtime complexity for such characterization becomes of the order of number of devices in the cell and the number of simulations required can easily become infeasible. We analyze the fluctuations in switching and non-switching devices and their impact on delay variations. Using these properties of the devices, we propose a clustering approach to characterize for cell's delay variations due to intra-cell mismatch variations. The proposed approach results in as much as 12X runtime improvements with acceptable accuracy, compared with Monte Carlo simulations. We show that this approach ensures an upper-bound on the results while keeping the number of simulations for each cell independent of the number of devices.
{"title":"Characterization of Standard Cells for Intra-Cell Mismatch Variations","authors":"S. Sundareswaran, J. Abraham, A. Ardelea, R. Panda","doi":"10.1109/ISQED.2008.11","DOIUrl":"https://doi.org/10.1109/ISQED.2008.11","url":null,"abstract":"With the adoption of statistical timing across industry, there is a need to characterize all gates/cells in a digital library for delay variations (referred to as, statistical characterization). Statistical characterization need to be performed efficiently with acceptable accuracy as a function of several process and environment parameter variations. In this paper, we propose an approach to consider intra-cell process mismatch variations to characterize a cell's delay and output transition time (output slew) variations. A straightforward approach to address this problem is to model these mismatch variations by characterizing for each device fluctuation separately. However, the runtime complexity for such characterization becomes of the order of number of devices in the cell and the number of simulations required can easily become infeasible. We analyze the fluctuations in switching and non-switching devices and their impact on delay variations. Using these properties of the devices, we propose a clustering approach to characterize for cell's delay variations due to intra-cell mismatch variations. The proposed approach results in as much as 12X runtime improvements with acceptable accuracy, compared with Monte Carlo simulations. We show that this approach ensures an upper-bound on the results while keeping the number of simulations for each cell independent of the number of devices.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-02-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132691702","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A novel method to characterize CMOS process fluctuations in subthreshold current mirrors (SCM) is reported in this paper. The proposed model is succinct in methodology and calculation complexity comparing to the reported statistical models, however, provides favorable estimations of CMOS process fluctuations on the SCM circuit, which makes it being promising for engineering applications. The model statistically abstracts physical parameters, which depend on IC process, into random variables with certain mean values and standard deviations, while aggregating all the random impacts into a discrete martingale. The correctness of proposed method is experimentally verified by an SCM circuit implemented in SMIC 0.18 mum CMOS 1P6M mixed signal process with a conversion factor of 100 over an input range from 100 pA to 1 muA. The proposed theory successfully predicted the ~plusmn10% of die-to-die fluctuation measured in experiment, and also suggested the ~ 1 mV of threshold voltage standard deviation over a single die, which meets the process parameters suggested by the design kit from the foundry. The deviations between calculated probabilities and measured data are less than 8%. Meanwhile, pertinent suggestions to high fluctuation tolerance subthreshold analog circuits design are also made and discussed.
本文报道了一种表征亚阈值电流镜(SCM)中CMOS工艺波动的新方法。与已有的统计模型相比，所提出的模型在方法上简洁，计算复杂度低，但能很好地估计CMOS工艺在单片机电路上的波动，具有工程应用前景。该模型将依赖于集成电路过程的物理参数统计抽象为具有一定均值和标准差的随机变量，并将所有随机影响聚合为离散鞅。通过实验验证了该方法的正确性，该电路采用中芯0.18 μ m CMOS 1P6M混合信号处理，转换系数为100，输入范围为100pa ~ 1mua。该理论成功地预测了实验中测量到的~±10%的模间波动，并提出了单模上的阈值电压标准偏差~ 1 mV，符合铸造厂设计套件提出的工艺参数。计算概率与实测数据的偏差小于8%。同时，对高波动容限亚阈值模拟电路的设计提出了针对性的建议。
{"title":"A Statistical Characterization of CMOS Process Fluctuations in Subthreshold Current Mirrors","authors":"Lei Zhang, Zhiping Yu, Xiangqing He","doi":"10.1109/ISQED.2008.44","DOIUrl":"https://doi.org/10.1109/ISQED.2008.44","url":null,"abstract":"A novel method to characterize CMOS process fluctuations in subthreshold current mirrors (SCM) is reported in this paper. The proposed model is succinct in methodology and calculation complexity comparing to the reported statistical models, however, provides favorable estimations of CMOS process fluctuations on the SCM circuit, which makes it being promising for engineering applications. The model statistically abstracts physical parameters, which depend on IC process, into random variables with certain mean values and standard deviations, while aggregating all the random impacts into a discrete martingale. The correctness of proposed method is experimentally verified by an SCM circuit implemented in SMIC 0.18 mum CMOS 1P6M mixed signal process with a conversion factor of 100 over an input range from 100 pA to 1 muA. The proposed theory successfully predicted the ~plusmn10% of die-to-die fluctuation measured in experiment, and also suggested the ~ 1 mV of threshold voltage standard deviation over a single die, which meets the process parameters suggested by the design kit from the foundry. The deviations between calculated probabilities and measured data are less than 8%. Meanwhile, pertinent suggestions to high fluctuation tolerance subthreshold analog circuits design are also made and discussed.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116949733","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Q. Ding, Yu Wang, Hui Wang, Rong Luo, Huazhong Yang
It is expected that the soft error rate (SER) of combinational logic will increase significantly. Previous solutions to mitigate soft errors in combinational logic suffer from delay penalty or area/power overhead. In this paper, we proposed an output remapping technique to reduce SER of critical paths. Experimental results show up to about 20X increase in Qcritical. So the SER is reduced significantly. This method does not introduce any delay penalty. The area/power overhead is limited as well. The output remapping method is based on our novel glitch width model. The analysis shows that output remapping technique works well along with technology scaling.
{"title":"Output Remapping Technique for Soft-Error Rate Reduction in Critical Paths","authors":"Q. Ding, Yu Wang, Hui Wang, Rong Luo, Huazhong Yang","doi":"10.1109/ISQED.2008.86","DOIUrl":"https://doi.org/10.1109/ISQED.2008.86","url":null,"abstract":"It is expected that the soft error rate (SER) of combinational logic will increase significantly. Previous solutions to mitigate soft errors in combinational logic suffer from delay penalty or area/power overhead. In this paper, we proposed an output remapping technique to reduce SER of critical paths. Experimental results show up to about 20X increase in Qcritical. So the SER is reduced significantly. This method does not introduce any delay penalty. The area/power overhead is limited as well. The output remapping method is based on our novel glitch width model. The analysis shows that output remapping technique works well along with technology scaling.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122305497","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Summary form only given. Test has long been recognized as the bridge between design and manufacturing. However, innovation and deep integration in design and test tools has not kept pace with the consumerization of electronics and the rapidly evolving nanometer IC design and manufacturing. As a result, the full potential of Test has not been harnessed by the mainstream semiconductor community.The consumerization of electronics places significant new demands on low power, correctness and time-to-volume production.The rapid advances in nanometer technologies pose additional set of challenges due to the advanced physics effects and higher scales of transistor integration. The EDA industry needs to establish a new paradigm and a "deep integration" to meet these challenges. During the design phase, a power-aware DFT architecture must integrate tightly with low power design and implementation flow. Later, during the manufacturing phase, the benefits of DFT must be seamlessly harnessed for rapid scan diagnostics based yield learning using not only logic information from the design database but also using layout timing and power information. This keynote will discuss these challenges and possible solutions and scenarios.
{"title":"Plenary Speech 2P1: Consumerization of Electronics and Nanometer Technologies: Implications for Manufacturing Test","authors":"S. Taneja","doi":"10.1109/ISQED.2008.178","DOIUrl":"https://doi.org/10.1109/ISQED.2008.178","url":null,"abstract":"Summary form only given. Test has long been recognized as the bridge between design and manufacturing. However, innovation and deep integration in design and test tools has not kept pace with the consumerization of electronics and the rapidly evolving nanometer IC design and manufacturing. As a result, the full potential of Test has not been harnessed by the mainstream semiconductor community.The consumerization of electronics places significant new demands on low power, correctness and time-to-volume production.The rapid advances in nanometer technologies pose additional set of challenges due to the advanced physics effects and higher scales of transistor integration. The EDA industry needs to establish a new paradigm and a \"deep integration\" to meet these challenges. During the design phase, a power-aware DFT architecture must integrate tightly with low power design and implementation flow. Later, during the manufacturing phase, the benefits of DFT must be seamlessly harnessed for rapid scan diagnostics based yield learning using not only logic information from the design database but also using layout timing and power information. This keynote will discuss these challenges and possible solutions and scenarios.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"33 1-2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116717565","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Design for manufacturability and yield has becomes a major issue for advanced VLSI technology nodes. The demand for a yield prediction capability has been growing significantly. Unfortunately, systematic yield prediction and analysis is still behind in both research and availability of commercial tools. A major reason for that is the high dependency of such research on hard to come by data from fabs. Thus a new approach that limits this dependency is needed. In this paper, we propose a novel and practical approach that enables systematic yield prediction with limited fab information and data. This approach is based on the information of hotspot definitions and their yield scores. The required inputs are more practical and realistic and less confidential. The dependency on the fab data is minimal. In this approach, we propose an algorithm that properly incorporates spatial correlations between yield variables when computing full chip total yield. The predicted total yield score is accurate and robust. We further demonstrate the high level of accuracy by both theory and simulation.
{"title":"Hotspot Based Yield Prediction with Consideration of Correlations","authors":"Qing Su, C. Chiang, J. Kawa","doi":"10.1109/ISQED.2008.30","DOIUrl":"https://doi.org/10.1109/ISQED.2008.30","url":null,"abstract":"Design for manufacturability and yield has becomes a major issue for advanced VLSI technology nodes. The demand for a yield prediction capability has been growing significantly. Unfortunately, systematic yield prediction and analysis is still behind in both research and availability of commercial tools. A major reason for that is the high dependency of such research on hard to come by data from fabs. Thus a new approach that limits this dependency is needed. In this paper, we propose a novel and practical approach that enables systematic yield prediction with limited fab information and data. This approach is based on the information of hotspot definitions and their yield scores. The required inputs are more practical and realistic and less confidential. The dependency on the fab data is minimal. In this approach, we propose an algorithm that properly incorporates spatial correlations between yield variables when computing full chip total yield. The predicted total yield score is accurate and robust. We further demonstrate the high level of accuracy by both theory and simulation.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128242614","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Inductive fault analysis techniques examine the physical geometry of a design to identify potential defect sites. Since traditional methodologies for test generation, fault simulation, and diagnosis rely on logic-level models of the circuit under test, the behavior of a circuit node within a standard cell is not easily modeled since it does not always map directly to a logic-level signal. A significant percentage of defects, however, involves these internal nodes and therefore cannot be ignored. Also, due to the potentially complex behavior of feedback bridges, many defects that cause structural feedback are ignored. We propose a methodology to create a mapping between the physical nodes of a standard cell and the logic level. By identifying appropriate fault activation and error propagation conditions for each internal node, accurate fault models can be formulated. We also describe a strategy for modeling feedback bridges that enables the use of traditional test tools.
{"title":"Automated Standard Cell Library Analysis for Improved Defect Modeling","authors":"J. G. Brown, Shawn Blanton","doi":"10.1109/ISQED.2008.169","DOIUrl":"https://doi.org/10.1109/ISQED.2008.169","url":null,"abstract":"Inductive fault analysis techniques examine the physical geometry of a design to identify potential defect sites. Since traditional methodologies for test generation, fault simulation, and diagnosis rely on logic-level models of the circuit under test, the behavior of a circuit node within a standard cell is not easily modeled since it does not always map directly to a logic-level signal. A significant percentage of defects, however, involves these internal nodes and therefore cannot be ignored. Also, due to the potentially complex behavior of feedback bridges, many defects that cause structural feedback are ignored. We propose a methodology to create a mapping between the physical nodes of a standard cell and the logic level. By identifying appropriate fault activation and error propagation conditions for each internal node, accurate fault models can be formulated. We also describe a strategy for modeling feedback bridges that enables the use of traditional test tools.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128994894","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-03-17DOI: 10.1109/ISQED.2008.4479838
G. Fey, R. Drechsler
Correct input/output behavior of circuits in presence of internal malfunctions becomes more and more important. But reliable and efficient methods to measure this robustness are not available yet. In this paper a formal measure for the robustness of a circuit is introduced. Then, a first algorithm to determine the robustness is presented. This is done by reducing the problem either to sequential equivalence checking or to a sequence of property checking instances. The technique also identifies those parts of the circuit that are not robust from a functional point of view and therefore have to be hardened during layout.
{"title":"A Basis for Formal Robustness Checking","authors":"G. Fey, R. Drechsler","doi":"10.1109/ISQED.2008.4479838","DOIUrl":"https://doi.org/10.1109/ISQED.2008.4479838","url":null,"abstract":"Correct input/output behavior of circuits in presence of internal malfunctions becomes more and more important. But reliable and efficient methods to measure this robustness are not available yet. In this paper a formal measure for the robustness of a circuit is introduced. Then, a first algorithm to determine the robustness is presented. This is done by reducing the problem either to sequential equivalence checking or to a sequence of property checking instances. The technique also identifies those parts of the circuit that are not robust from a functional point of view and therefore have to be hardened during layout.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126886182","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Summary form only given. Variability due to manufacturing, environmental and aging uncertainties constitutes one of the major challenges in continuing CMOS scaling. Worst-case design is simply not feasible any more.This presentation will describe how statistical timing techniques can be used to reduce pessimism, achieve full-chip and full-process coverage, and enable robust design practices. A practical ASIC methodology based on statistical timing will be described. Robust optimization techniques will be discussed. Variability makes post-manufacturing testing a daunting task. Process coverage is a new metric that must be considered. Statistical techniques to improve quality in the context of at-speed test will be presented. Key research initiatives required to achieve elements of a statistical design flow will be described.
{"title":"Plenary Speech 2P2: Statistical Techniques to Achieve Robustness and Quality","authors":"C. Visweswariah","doi":"10.1109/ISQED.2008.179","DOIUrl":"https://doi.org/10.1109/ISQED.2008.179","url":null,"abstract":"Summary form only given. Variability due to manufacturing, environmental and aging uncertainties constitutes one of the major challenges in continuing CMOS scaling. Worst-case design is simply not feasible any more.This presentation will describe how statistical timing techniques can be used to reduce pessimism, achieve full-chip and full-process coverage, and enable robust design practices. A practical ASIC methodology based on statistical timing will be described. Robust optimization techniques will be discussed. Variability makes post-manufacturing testing a daunting task. Process coverage is a new metric that must be considered. Statistical techniques to improve quality in the context of at-speed test will be presented. Key research initiatives required to achieve elements of a statistical design flow will be described.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130672987","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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