VLSI complexity of threshold gate COMPARISON

Abstract

The paper overviews recent developments concerning optimal (from the point of view of size and depth) implementations of the Boolean function COMPARISON using feedforward neural networks made of threshold gates. We detail a class of solutions which covers another particular solution, and spans from constant to logarithmic depths. These circuit complexity results are supplemented by fresh VLSI complexity results having applications to hardware implementations of neural networks and to VLSI-friendly learning algorithms. In order to estimate the area (A) and the delay (T), as well as the classical AT/sup 2/, we use the following 'cost functions': (i) the connectivity (i.e., sum of fan-ins) and the number-of-bits for representing the weights and thresholds are used to approximate the area; while (ii) the fan-ins and the length of the wires are used for closer estimates of the delay. Such approximations allow us to compare the different solutions-which present very interesting fan-in dependent depth-size and area-delay tradeoffs-with respect to AT/sup 2/.