A BIST method for TSVs pre-bond test

Abstract

In this paper we present a Built-In-Self-Test (BIST) method dedicated to pre-bond testing of TSVs in 3D stacked integrated circuits. The test method aims to detect full-open and pin-hole defects by measuring the discharge delay of TSVs' equivalent capacitance. The paper presents an original solution for monitoring the discharge delay of the TSV under test independently of the process variations. Simulation-based results shows that the method is robust w.r.t these variations. The proposed BIST circuitry is small enough to be inserted in the available area between the TSVs.