Pub Date : 2013-12-01DOI: 10.1109/IDT.2013.6727128
S. Carlo, Giulio Gambardella, T. H. Bao, P. Prinetto, Daniele Rolfo, Pascal Trotta
Dynamic Partial Reconfiguration allows to dynamically change the behaviour of a portion of the FPGAs by downloading new information in the configuration memory of the device. Since modern Systems-on-Programmable-Chips (SoPCs) make extensive use of this feature, many reconfigurable area are placed in the device, with several configurations for each area. This comes at a cost in terms of dependability of the system and of memory occupation. The proposed methodology focuses on increasing the dependability of partially reconfigurable systems by safely storing compressed configuration data inside the FPGA.
{"title":"ZipStream: Improving dependability in dynamic partial reconfiguration","authors":"S. Carlo, Giulio Gambardella, T. H. Bao, P. Prinetto, Daniele Rolfo, Pascal Trotta","doi":"10.1109/IDT.2013.6727128","DOIUrl":"https://doi.org/10.1109/IDT.2013.6727128","url":null,"abstract":"Dynamic Partial Reconfiguration allows to dynamically change the behaviour of a portion of the FPGAs by downloading new information in the configuration memory of the device. Since modern Systems-on-Programmable-Chips (SoPCs) make extensive use of this feature, many reconfigurable area are placed in the device, with several configurations for each area. This comes at a cost in terms of dependability of the system and of memory occupation. The proposed methodology focuses on increasing the dependability of partially reconfigurable systems by safely storing compressed configuration data inside the FPGA.","PeriodicalId":446826,"journal":{"name":"2013 8th IEEE Design and Test Symposium","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121802982","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/IDT.2013.6727111
Omar Samir, Moustafa Kassem, Mohammed Sameh, Sarah Aly, M. Rizk, Mohamed Abdelsalam, A. Salem
This paper aims to develop an Open Verification Methodology (OVM) environment to support testing of memory protocol standards and verify their operation using coverage driven verification (CDV) and constrained random testing (CRT). The objective is to achieve most of the verification plan goals with less time and effort and to create reusable verification environment components. We demonstrate the robustness of this approach using LPDDR3 memory protocol as a case study.
{"title":"A novel approach for functional verification of memory protocol standard","authors":"Omar Samir, Moustafa Kassem, Mohammed Sameh, Sarah Aly, M. Rizk, Mohamed Abdelsalam, A. Salem","doi":"10.1109/IDT.2013.6727111","DOIUrl":"https://doi.org/10.1109/IDT.2013.6727111","url":null,"abstract":"This paper aims to develop an Open Verification Methodology (OVM) environment to support testing of memory protocol standards and verify their operation using coverage driven verification (CDV) and constrained random testing (CRT). The objective is to achieve most of the verification plan goals with less time and effort and to create reusable verification environment components. We demonstrate the robustness of this approach using LPDDR3 memory protocol as a case study.","PeriodicalId":446826,"journal":{"name":"2013 8th IEEE Design and Test Symposium","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123742949","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/IDT.2013.6727095
L. Russo, Giuseppe Airò Farulla, Marco Indaco, Stefano Rosa, Daniele Rolfo, B. Bona
The paper presents a method aiming at improving the reliability of Simultaneous Localization And Mapping (SLAM) approaches based on vision systems. Classical SLAM approaches treat camera capturing time as negligible, and the recorded frames as sharp and well-defined, but this hypothesis does not hold true when the camera is moving too fast. In such cases, in fact, frames may be severely degraded by motion blur, making features matching task a difficult operation. The method here presented is based on a novel approach that combines the benefits of a fully probabilistic SLAM algorithm with the basic ideas behind modern motion blur handling algorithms. Whereby the Kalman Filter, the new approach predicts the best possible blur Point Spread Function (PSF) for each feature and performs matching using also this information.
{"title":"Blurring prediction in monocular SLAM","authors":"L. Russo, Giuseppe Airò Farulla, Marco Indaco, Stefano Rosa, Daniele Rolfo, B. Bona","doi":"10.1109/IDT.2013.6727095","DOIUrl":"https://doi.org/10.1109/IDT.2013.6727095","url":null,"abstract":"The paper presents a method aiming at improving the reliability of Simultaneous Localization And Mapping (SLAM) approaches based on vision systems. Classical SLAM approaches treat camera capturing time as negligible, and the recorded frames as sharp and well-defined, but this hypothesis does not hold true when the camera is moving too fast. In such cases, in fact, frames may be severely degraded by motion blur, making features matching task a difficult operation. The method here presented is based on a novel approach that combines the benefits of a fully probabilistic SLAM algorithm with the basic ideas behind modern motion blur handling algorithms. Whereby the Kalman Filter, the new approach predicts the best possible blur Point Spread Function (PSF) for each feature and performs matching using also this information.","PeriodicalId":446826,"journal":{"name":"2013 8th IEEE Design and Test Symposium","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128115123","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/IDT.2013.6727118
A. Bengueddach, B. Senouci, S. Niar, B. Beldjilali
In order to meet the ever-increasing computing requirement in embedded market, multiprocessor chips were proposed as the best way out. In this work we investigate the estimation of the energy consumption in embedded MPSoC system. One of the efficient solutions to reduce the energy consumption is to reconfigure the caches memories. This approach was applied for one cache level/one processor architecture. The main contribution of this paper is to explore two level data cache (L1/L2) multiprocessor architecture by estimating the energy consumption. Using a simulation platform (Multi2Simj, we first built a multiprocessor architecture, and then we propose a new modified CPACT algorithm that tunes the two-level caches memory hierarchy (L1 & L2). The caches tuning approach is based on three parameters: cache size, line size, and associativity. In this approach, and in order to find the best cache configuration, the software application is divided into several intervals and we generate automatically the best cache configuration for each interval of the application. Finally, the approach is validated using a set of open source benchmarks, Spec2006, Splash-2 and MediaBench and we discuss the performance in terms of speedup and energy reduction.
{"title":"Energy consumption in reconfigurable mpsoc architecture: Two-level caches optimization oriented approach","authors":"A. Bengueddach, B. Senouci, S. Niar, B. Beldjilali","doi":"10.1109/IDT.2013.6727118","DOIUrl":"https://doi.org/10.1109/IDT.2013.6727118","url":null,"abstract":"In order to meet the ever-increasing computing requirement in embedded market, multiprocessor chips were proposed as the best way out. In this work we investigate the estimation of the energy consumption in embedded MPSoC system. One of the efficient solutions to reduce the energy consumption is to reconfigure the caches memories. This approach was applied for one cache level/one processor architecture. The main contribution of this paper is to explore two level data cache (L1/L2) multiprocessor architecture by estimating the energy consumption. Using a simulation platform (Multi2Simj, we first built a multiprocessor architecture, and then we propose a new modified CPACT algorithm that tunes the two-level caches memory hierarchy (L1 & L2). The caches tuning approach is based on three parameters: cache size, line size, and associativity. In this approach, and in order to find the best cache configuration, the software application is divided into several intervals and we generate automatically the best cache configuration for each interval of the application. Finally, the approach is validated using a set of open source benchmarks, Spec2006, Splash-2 and MediaBench and we discuss the performance in terms of speedup and energy reduction.","PeriodicalId":446826,"journal":{"name":"2013 8th IEEE Design and Test Symposium","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131758055","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/IDT.2013.6727110
K. Khalil, M. Abbas, M. Abdelgawad
This paper presents a low delay dispersion comparator for low cost level-crossing Analog-to-Digital converters. The conventional comparator circuit is modified by adding a variable driving-current block (VDCB) which is used such that it supplies the output node of the differential amplifier with a current that is inversely proportional with the level of input signal. The modification incurs small area overhead (only three transistors) compared with the previous works. The proposed comparator is designed in order to reduce the propagation delay dispersion caused by variable input overdrive and the common mode level. The proposed circuit is implemented in 130nm technology. The simulation results show that the overdrive-related propagation delay dispersion of the proposed technique is 27% of its counterpart in the conventional comparator for an input frequency up to 600MHz. The active area of the technique140.2 μm2 and the power consumption is 250 μW at 200MHz.
{"title":"A low propagation delay dispersion comparator for low cost level-crossing ADCs","authors":"K. Khalil, M. Abbas, M. Abdelgawad","doi":"10.1109/IDT.2013.6727110","DOIUrl":"https://doi.org/10.1109/IDT.2013.6727110","url":null,"abstract":"This paper presents a low delay dispersion comparator for low cost level-crossing Analog-to-Digital converters. The conventional comparator circuit is modified by adding a variable driving-current block (VDCB) which is used such that it supplies the output node of the differential amplifier with a current that is inversely proportional with the level of input signal. The modification incurs small area overhead (only three transistors) compared with the previous works. The proposed comparator is designed in order to reduce the propagation delay dispersion caused by variable input overdrive and the common mode level. The proposed circuit is implemented in 130nm technology. The simulation results show that the overdrive-related propagation delay dispersion of the proposed technique is 27% of its counterpart in the conventional comparator for an input frequency up to 600MHz. The active area of the technique140.2 μm2 and the power consumption is 250 μW at 200MHz.","PeriodicalId":446826,"journal":{"name":"2013 8th IEEE Design and Test Symposium","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133649545","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/IDT.2013.6727138
Huthaifa Obeidat, R. Abd‐Alhameed, J. Noras, S. Zhu, T. Ghazaany, N. Ali, E. Elkhazmi
A comparison between two indoor localization algorithms using received signal strength is carried out. The first algorithm is the vector algorithm; the second is the matrix algorithm. The comparison considered the effects of the reference points, the access point, and the frequency on the accuracy of the localization process. The experiments were carried out using ray tracing software and MATLAB. This paper justifies the use of adopting the matrix algorithm.
{"title":"Indoor localization using received signal strength","authors":"Huthaifa Obeidat, R. Abd‐Alhameed, J. Noras, S. Zhu, T. Ghazaany, N. Ali, E. Elkhazmi","doi":"10.1109/IDT.2013.6727138","DOIUrl":"https://doi.org/10.1109/IDT.2013.6727138","url":null,"abstract":"A comparison between two indoor localization algorithms using received signal strength is carried out. The first algorithm is the vector algorithm; the second is the matrix algorithm. The comparison considered the effects of the reference points, the access point, and the frequency on the accuracy of the localization process. The experiments were carried out using ray tracing software and MATLAB. This paper justifies the use of adopting the matrix algorithm.","PeriodicalId":446826,"journal":{"name":"2013 8th IEEE Design and Test Symposium","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125743947","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/IDT.2013.6727086
K. Anoh, E. Elkazmi, R. Abd‐Alhameed, O. Madubuko, M. Bin-Melha, S. R. Jones, T. Ghazaany
Beamforming is used to achieve diversity gain. It is a technique in diversity to remedy power penalty due to channel fading. The beam-weights for multi-antenna system are evaluated for two different approaches. These weights are then used to weight the signal beams of each transmit antenna branch. Results reveal that by exploiting the transmit channel substructures exposed by the singular vector decomposition algorithm, the capacity of a multi-antenna system can be enhanced.
{"title":"Improved multi-antenna system capacity using beamformer weights","authors":"K. Anoh, E. Elkazmi, R. Abd‐Alhameed, O. Madubuko, M. Bin-Melha, S. R. Jones, T. Ghazaany","doi":"10.1109/IDT.2013.6727086","DOIUrl":"https://doi.org/10.1109/IDT.2013.6727086","url":null,"abstract":"Beamforming is used to achieve diversity gain. It is a technique in diversity to remedy power penalty due to channel fading. The beam-weights for multi-antenna system are evaluated for two different approaches. These weights are then used to weight the signal beams of each transmit antenna branch. Results reveal that by exploiting the transmit channel substructures exposed by the singular vector decomposition algorithm, the capacity of a multi-antenna system can be enhanced.","PeriodicalId":446826,"journal":{"name":"2013 8th IEEE Design and Test Symposium","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129342377","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/IDT.2013.6727076
Marco Desogus, M. Reorda, L. Sterpone, V. Avantaggiati, G. Audisio, M. Sabatini
Due to the growing complexity of automotive systems, including various modules (e.g., microcontrollers, DSPs, memories and IP cores), validation and debug have become increasingly complex, with consequent impact on time-to-market and quality. In this paper we propose a novel flow for hardware and software validation and debug through the use of an FPGA-based emulation platform, which provides a valuable support for these important phases of the development flow. The same emulation platform is also able to support faults injection in the device under validation. Fault injection is intended not only to provide an evaluation of the system fault tolerance, but also to support the debug of the embedded fault tolerance mechanisms. Experimental results on a real industrial case study allow to evaluate the effectiveness and costs of the proposed solution.
{"title":"Validation and robustness assessment of an automotive system","authors":"Marco Desogus, M. Reorda, L. Sterpone, V. Avantaggiati, G. Audisio, M. Sabatini","doi":"10.1109/IDT.2013.6727076","DOIUrl":"https://doi.org/10.1109/IDT.2013.6727076","url":null,"abstract":"Due to the growing complexity of automotive systems, including various modules (e.g., microcontrollers, DSPs, memories and IP cores), validation and debug have become increasingly complex, with consequent impact on time-to-market and quality. In this paper we propose a novel flow for hardware and software validation and debug through the use of an FPGA-based emulation platform, which provides a valuable support for these important phases of the development flow. The same emulation platform is also able to support faults injection in the device under validation. Fault injection is intended not only to provide an evaluation of the system fault tolerance, but also to support the debug of the embedded fault tolerance mechanisms. Experimental results on a real industrial case study allow to evaluate the effectiveness and costs of the proposed solution.","PeriodicalId":446826,"journal":{"name":"2013 8th IEEE Design and Test Symposium","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128840479","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/IDT.2013.6727139
O. Hammami, Xinyu Li
Rapid advances of silicon and parallel processing technologies allow the building of multiprocessor systems-on-chip (MPSoCs). Cache coherency problem becomes one of the major design issues to improve the performance of multiprocessor. We first realize a directory based cache coherency scheme of Network on Chip (NoC) based MPSOC implemented on FPGA using the industrial standard protocol of OCP-IP. In this paper we present the system architecture and implementation results which shows that NoC based coherency system is well scalable. JTAG and PCI based debug system are developed for visualizing the application execution of our NoC based MPSoC cache coherency system.
{"title":"NOC based MPSOC directory based cache coherency with OCP-IP protocol","authors":"O. Hammami, Xinyu Li","doi":"10.1109/IDT.2013.6727139","DOIUrl":"https://doi.org/10.1109/IDT.2013.6727139","url":null,"abstract":"Rapid advances of silicon and parallel processing technologies allow the building of multiprocessor systems-on-chip (MPSoCs). Cache coherency problem becomes one of the major design issues to improve the performance of multiprocessor. We first realize a directory based cache coherency scheme of Network on Chip (NoC) based MPSOC implemented on FPGA using the industrial standard protocol of OCP-IP. In this paper we present the system architecture and implementation results which shows that NoC based coherency system is well scalable. JTAG and PCI based debug system are developed for visualizing the application execution of our NoC based MPSoC cache coherency system.","PeriodicalId":446826,"journal":{"name":"2013 8th IEEE Design and Test Symposium","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121195851","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/IDT.2013.6727117
K. Datta, I. Sengupta, H. Rahaman, R. Drechsler
The area of reversible circuit synthesis has become very important in recent years with the growing emphasis on low-power design and quantum computation. Many synthesis approaches have been reported over the last two decades. For small functions exact solutions can be computed. Otherwise, heuristics have to be applied that are either based on transformations or a direct mapping from a given data structure. Recently, it was shown that significant reduction in the cost of the synthesized circuits can be obtained, if the ordering of the output lines is changed. The drawback of the approach was that it can only be applied to smaller sized circuits. In this paper, an evolutionary approach for obtaining a good ordering of the output variables is proposed, which can be used for larger sized circuits as well. The method does not require explicit synthesis of the reversible circuit netlist. Experimental results are shown with respect to a transformation based synthesis tool. Reductions of up to 98% can be observed with an average reduction of 64.4 % for larger circuits.
{"title":"An evolutionary approach to reversible logic synthesis using output permutation","authors":"K. Datta, I. Sengupta, H. Rahaman, R. Drechsler","doi":"10.1109/IDT.2013.6727117","DOIUrl":"https://doi.org/10.1109/IDT.2013.6727117","url":null,"abstract":"The area of reversible circuit synthesis has become very important in recent years with the growing emphasis on low-power design and quantum computation. Many synthesis approaches have been reported over the last two decades. For small functions exact solutions can be computed. Otherwise, heuristics have to be applied that are either based on transformations or a direct mapping from a given data structure. Recently, it was shown that significant reduction in the cost of the synthesized circuits can be obtained, if the ordering of the output lines is changed. The drawback of the approach was that it can only be applied to smaller sized circuits. In this paper, an evolutionary approach for obtaining a good ordering of the output variables is proposed, which can be used for larger sized circuits as well. The method does not require explicit synthesis of the reversible circuit netlist. Experimental results are shown with respect to a transformation based synthesis tool. Reductions of up to 98% can be observed with an average reduction of 64.4 % for larger circuits.","PeriodicalId":446826,"journal":{"name":"2013 8th IEEE Design and Test Symposium","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125087371","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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