Impact of device design parameters on VDSAT and analog performance of TFETs

Abstract

We report the impact of device design parameters on the saturation voltages (VDSAT) and thereby on analog performance of the Tunnel FETs (TFET). As the drain bias (VDS) increases, the device initially enters a soft saturation and later into a deep saturation state, both at a constant difference between the gate-drain bias (VGD)· An increase in source (drain) doping decreases (increases) the soft saturation voltage. The short channel lengths degrade the saturation in the TFETs. Agate-drain underlapcauses early onset of the saturation in TFETs, while, a reduction in the nanowire diameter delays the saturation. The output resistance (Ro), transconductance (gm), and intrinsic gain (gm×Ro) increase when the device enters in soft saturation and attain a maxi mum in the deep saturation state. Our work elucidates the physics behind above observations, and provides insights into the device design of the TFETs.