Reduction of common mode voltage for cascaded 3-level inverter using SVPWM

Abstract

The common mode voltage (CMV) generated by multilevel inverters can be reduced. This paper presents a Spacevector pulse width modulation (SVPWM) approach for cascaded 3-level inverters to reduce common mode voltage. Conventional 3-level pulse width modulated (PWM) inverters are widely known for producing high-frequency commonmode voltages with high dv/dt. Motor shaft voltages and bearing currents can be caused by common mode voltages. In this work, to reduce common mode voltage, partial CMV elimination technique is used. In this method the redundant states of 3-level inverter having CMV less than or equal to Vdc/6 are only used and the redundant states having CMV greater than Vdc/6 are avoided by implementing SVPWM, where Vdc is the input DC voltage of inverter. A simulation of an dc SVM technique to reduce common mode voltage is implemented. Bearing voltages, bearing currents and total harmonic distortion (THD) are evaluated in the performance analysis. The results will prove the reduction of CMV with the proposed technique compared to conventional SVPWM.