Kyoung-Jun Moon, Dong-Ryeol Oh, Younghyo Park, Kyung-Hoon Lee, Sun-Jae Park, Sungno Lee, H. Hwang, H. Shin, Young-Jae Cho, Michael Choi, Jongshin Shin
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引用次数: 5
Abstract
A 12b 10GS/s 16-channel time-interleaved (TI) ADC with cascaded input buffers, 625MS/s voltage-current (V-I) pipelined SAR ADCs and a digital processing timing-skew background calibration is proposed. A prototype 10GS/s TI ADC in 5nm FinFET achieves 48dB SNDR at the Nyquist input with 625mW power consumption, leading to a FoMWalden of 305fJ/c-s.
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