An analog checker with dynamically adjustable error threshold for fully differential circuits

Abstract

We present a novel analog checker that adjusts dynamically the error threshold to the magnitude of its input signals. We demonstrate that this property is crucial for accurate concurrent error detection in analog circuits. Dynamic error threshold adjustment is achieved by regulating the bias point of the output stage inverters of the checker, which provide a digital indication of potential errors in the circuit under test. We discuss the theoretical foundation and we present simulations that validate the underlying principle of the design. As compared to previous solutions, the proposed checker reduces the incurred overhead, while significantly enhancing the quality of concurrent error detection.