Pub Date : 2004-06-01DOI: 10.1109/VTEST.2003.1197649
A. El-Maleh, K. Al-Utaibi
Testing systems-on-a-chip (SOC) involves applying huge amounts of test data, which is stored in the tester memory and then transferred to the circuit under test (CUT) during test application. Therefore, practical techniques, such as test compression and compaction, are required to reduce the amount of test data in order to reduce both the total testing time and the memory requirements for the tester Relaxing test sequences can improve the efficiency of both test compression and test compaction. In addition, the relaxation process can identify self-initializing test sequences for synchronous sequential circuits. In this paper we propose an efficient test relaxation technique for synchronous sequential circuits that maximizes the number of unspecified bits while maintaining the same fault coverage as the original test set.
{"title":"An efficient test relaxation technique for synchronous sequential circuits","authors":"A. El-Maleh, K. Al-Utaibi","doi":"10.1109/VTEST.2003.1197649","DOIUrl":"https://doi.org/10.1109/VTEST.2003.1197649","url":null,"abstract":"Testing systems-on-a-chip (SOC) involves applying huge amounts of test data, which is stored in the tester memory and then transferred to the circuit under test (CUT) during test application. Therefore, practical techniques, such as test compression and compaction, are required to reduce the amount of test data in order to reduce both the total testing time and the memory requirements for the tester Relaxing test sequences can improve the efficiency of both test compression and test compaction. In addition, the relaxation process can identify self-initializing test sequences for synchronous sequential circuits. In this paper we propose an efficient test relaxation technique for synchronous sequential circuits that maximizes the number of unspecified bits while maintaining the same fault coverage as the original test set.","PeriodicalId":292996,"journal":{"name":"Proceedings. 21st VLSI Test Symposium, 2003.","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134248206","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-04-01DOI: 10.1109/VTEST.2003.1197682
K. N. Patel, J. Hayes, I. Markov
Irreversible computation necessarily results in energy dissipation due to information loss. While small in comparison to the power consumption of today's VLSI circuits, if current trends continue this will be a critical issue in the near future. Reversible circuits offer an alternative that, in principle, allows computation with arbitrarily small energy dissipation. Furthermore, reversible circuits are essential components of quantum logic. We consider the problem of testing these circuits, and in particular generating efficient test sets. The reversibility property significantly simplifies the problem, which is generally hard for the irreversible case. We discuss conditions for a test set to be complete, give a number of practical constructions, and consider test sets for worst-case circuits. In addition, we formulate the problem of finding minimal test sets into an integer linear program (ILP) with binary variables. While this ILP method is infeasible for large circuits, we show that combining it with a circuit decomposition approach yields a practical alternative.
{"title":"Fault testing for reversible circuits","authors":"K. N. Patel, J. Hayes, I. Markov","doi":"10.1109/VTEST.2003.1197682","DOIUrl":"https://doi.org/10.1109/VTEST.2003.1197682","url":null,"abstract":"Irreversible computation necessarily results in energy dissipation due to information loss. While small in comparison to the power consumption of today's VLSI circuits, if current trends continue this will be a critical issue in the near future. Reversible circuits offer an alternative that, in principle, allows computation with arbitrarily small energy dissipation. Furthermore, reversible circuits are essential components of quantum logic. We consider the problem of testing these circuits, and in particular generating efficient test sets. The reversibility property significantly simplifies the problem, which is generally hard for the irreversible case. We discuss conditions for a test set to be complete, give a number of practical constructions, and consider test sets for worst-case circuits. In addition, we formulate the problem of finding minimal test sets into an integer linear program (ILP) with binary variables. While this ILP method is infeasible for large circuits, we show that combining it with a circuit decomposition approach yields a practical alternative.","PeriodicalId":292996,"journal":{"name":"Proceedings. 21st VLSI Test Symposium, 2003.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130407481","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-05-07DOI: 10.1109/VTEST.2003.1197654
Lei Li, K. Chakrabarty
We present a dictionary-based test data compression approach for reducing test data volume and testing time in SOCs. The proposed method is based on the use of a small number of ATE channels to deliver compressed test patterns from the tester to the chip and to drive a large number of internal scan chains in the circuit under test. Therefore, it is especially suitable for a reduced pin-count and low-cost DFT test environment, where a narrow interface between the tester and the SOC is desirable. The dictionary-based approach not only reduces testing time but it also eliminates the need for additional synchronization and handshaking between the SOC and the ATE. The dictionary entries are determined during the compression procedure by solving a variant of the well-known clique partitioning problem from graph theory. Experimental results for the ISCAS-89 benchmarks and representative test data from IBM show that the proposed method outperforms a number of recently-proposed test data compression techniques.
{"title":"Test data compression using dictionaries with fixed-length indices [SOC testing]","authors":"Lei Li, K. Chakrabarty","doi":"10.1109/VTEST.2003.1197654","DOIUrl":"https://doi.org/10.1109/VTEST.2003.1197654","url":null,"abstract":"We present a dictionary-based test data compression approach for reducing test data volume and testing time in SOCs. The proposed method is based on the use of a small number of ATE channels to deliver compressed test patterns from the tester to the chip and to drive a large number of internal scan chains in the circuit under test. Therefore, it is especially suitable for a reduced pin-count and low-cost DFT test environment, where a narrow interface between the tester and the SOC is desirable. The dictionary-based approach not only reduces testing time but it also eliminates the need for additional synchronization and handshaking between the SOC and the ATE. The dictionary entries are determined during the compression procedure by solving a variant of the well-known clique partitioning problem from graph theory. Experimental results for the ISCAS-89 benchmarks and representative test data from IBM show that the proposed method outperforms a number of recently-proposed test data compression techniques.","PeriodicalId":292996,"journal":{"name":"Proceedings. 21st VLSI Test Symposium, 2003.","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121295637","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-05-07DOI: 10.1109/VTEST.2003.1197656
Erik H. Volkerink, S. Mitra
The conventional LFSR reseeding technique for test data compression generates one test pattern from each LFSR seed. The seed size is determined by the maximum number of specified bits in a test pattern belonging to a given test set. However, for most practical designs the majority of test patterns have significantly fewer specified bits compared to the maximum. This limits the amount of compression that can be achieved with conventional reseeding. This paper presents a new reseeding technique that overcomes this problem by generating a single test pattern from multiple seeds and multiple test patterns from a single seed. The new reseeding technique is applied to two industrial designs, resulting in significant reduction in tester memory requirement and test application time compared to the conventional reseeding technique.
{"title":"Efficient seed utilization for reseeding based compression [logic testing]","authors":"Erik H. Volkerink, S. Mitra","doi":"10.1109/VTEST.2003.1197656","DOIUrl":"https://doi.org/10.1109/VTEST.2003.1197656","url":null,"abstract":"The conventional LFSR reseeding technique for test data compression generates one test pattern from each LFSR seed. The seed size is determined by the maximum number of specified bits in a test pattern belonging to a given test set. However, for most practical designs the majority of test patterns have significantly fewer specified bits compared to the maximum. This limits the amount of compression that can be achieved with conventional reseeding. This paper presents a new reseeding technique that overcomes this problem by generating a single test pattern from multiple seeds and multiple test patterns from a single seed. The new reseeding technique is applied to two industrial designs, resulting in significant reduction in tester memory requirement and test application time compared to the conventional reseeding technique.","PeriodicalId":292996,"journal":{"name":"Proceedings. 21st VLSI Test Symposium, 2003.","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123518685","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-05-07DOI: 10.1109/VTEST.2003.1197639
P. Wohl, L. Huisman
Scan and logic built-in self-test (BIST) are increasingly used to reduce test cost. In these test architectures, many internal signals are observed through a small number of output pins or into a small signature analyzer, requiring a combinational space compactor. This paper analyzes the basic requirements of compactors to support efficient test and diagnosis, focusing on practical compactors where all inputs have a fanout of two. We show how graph theory can be used to model compactors and design compactors with robust non-aliasing properties that have minimal area and delay overhead and are independent of the test set, the fault model, and the circuit tested.
{"title":"Analysis and design of optimal combinational compactors [logic test]","authors":"P. Wohl, L. Huisman","doi":"10.1109/VTEST.2003.1197639","DOIUrl":"https://doi.org/10.1109/VTEST.2003.1197639","url":null,"abstract":"Scan and logic built-in self-test (BIST) are increasingly used to reduce test cost. In these test architectures, many internal signals are observed through a small number of output pins or into a small signature analyzer, requiring a combinational space compactor. This paper analyzes the basic requirements of compactors to support efficient test and diagnosis, focusing on practical compactors where all inputs have a fanout of two. We show how graph theory can be used to model compactors and design compactors with robust non-aliasing properties that have minimal area and delay overhead and are independent of the test set, the fault model, and the circuit tested.","PeriodicalId":292996,"journal":{"name":"Proceedings. 21st VLSI Test Symposium, 2003.","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130045984","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-04-27DOI: 10.1109/VTEST.2003.1197633
Grzegorz Mrugalski, J. Rajski, J. Tyszer
This paper presents a new highly modular architecture of generators and compactors of test patterns. This structure has fewer levels of logic, smaller fan-out, reduced area, and operates at faster speed than external feedback LFSRs, internal feedback LFSRs, and cellular automata, all implementing the same characteristic polynomial.
{"title":"High speed ring generators and compactors of test data [logic IC test]","authors":"Grzegorz Mrugalski, J. Rajski, J. Tyszer","doi":"10.1109/VTEST.2003.1197633","DOIUrl":"https://doi.org/10.1109/VTEST.2003.1197633","url":null,"abstract":"This paper presents a new highly modular architecture of generators and compactors of test patterns. This structure has fewer levels of logic, smaller fan-out, reduced area, and operates at faster speed than external feedback LFSRs, internal feedback LFSRs, and cellular automata, all implementing the same characteristic polynomial.","PeriodicalId":292996,"journal":{"name":"Proceedings. 21st VLSI Test Symposium, 2003.","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117211694","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-04-27DOI: 10.1109/VTEST.2003.1197635
Ahmad A. Al-Yamani, S. Mitra, E. McCluskey
Reseeding is used to improve the fault coverage of pseudo-random testing. The seed corresponds to the initial state of the LFSR before filling the scan chain. The number of deterministic seeds required is directly proportional to the tester storage or hardware overhead requirement. In this paper, we present an algorithm for seed ordering to minimize the number of seeds required to cover a set of deterministic test patterns. Our technique is applicable whether seeds are loaded from the tester or encoded on chip. Simulations show that, when compared to random ordering, the technique reduces seed storage or hardware overhead by up to 80%. The seeds we use are deterministic so 100% SSF fault coverage can be achieved. Also, the technique we present is fault-model independent.
{"title":"BIST reseeding with very few seeds","authors":"Ahmad A. Al-Yamani, S. Mitra, E. McCluskey","doi":"10.1109/VTEST.2003.1197635","DOIUrl":"https://doi.org/10.1109/VTEST.2003.1197635","url":null,"abstract":"Reseeding is used to improve the fault coverage of pseudo-random testing. The seed corresponds to the initial state of the LFSR before filling the scan chain. The number of deterministic seeds required is directly proportional to the tester storage or hardware overhead requirement. In this paper, we present an algorithm for seed ordering to minimize the number of seeds required to cover a set of deterministic test patterns. Our technique is applicable whether seeds are loaded from the tester or encoded on chip. Simulations show that, when compared to random ordering, the technique reduces seed storage or hardware overhead by up to 80%. The seeds we use are deterministic so 100% SSF fault coverage can be achieved. Also, the technique we present is fault-model independent.","PeriodicalId":292996,"journal":{"name":"Proceedings. 21st VLSI Test Symposium, 2003.","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125517911","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-04-27DOI: 10.1109/VTEST.2003.1197664
Xiaoyun Sun, L. Kinney, B. Vinnakota
Dynamic Idd test methods have been shown to detect defects that escape other test techniques. Normal process variations decrease the fault coverage and affect the performance of dynamic Idd test techniques. A dynamic-current based test metric, Energy Consumption Ratio (ECR), has been proposed to address the process variation problem and has been validated through extensive simulations and applications on manufactured circuits. In this paper, we first discuss the problems in practical implementation of ECR tests on large-size circuits of advanced technology, e.g., increased circuit size and leakage current degrade ECR performance. We then propose two possible solutions: one is based on extensive statistical data analysis and another uses an enhanced scan design to partition the circuit. Experimental results from simulations and actual devices are included in this paper.
{"title":"Development of energy consumption ratio test","authors":"Xiaoyun Sun, L. Kinney, B. Vinnakota","doi":"10.1109/VTEST.2003.1197664","DOIUrl":"https://doi.org/10.1109/VTEST.2003.1197664","url":null,"abstract":"Dynamic Idd test methods have been shown to detect defects that escape other test techniques. Normal process variations decrease the fault coverage and affect the performance of dynamic Idd test techniques. A dynamic-current based test metric, Energy Consumption Ratio (ECR), has been proposed to address the process variation problem and has been validated through extensive simulations and applications on manufactured circuits. In this paper, we first discuss the problems in practical implementation of ECR tests on large-size circuits of advanced technology, e.g., increased circuit size and leakage current degrade ECR performance. We then propose two possible solutions: one is based on extensive statistical data analysis and another uses an enhanced scan design to partition the circuit. Experimental results from simulations and actual devices are included in this paper.","PeriodicalId":292996,"journal":{"name":"Proceedings. 21st VLSI Test Symposium, 2003.","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124367737","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-04-27DOI: 10.1109/VTEST.2003.1197652
M. Soma, W. Haileselassie, Jessica Sherrid
A method to measure time-varying phase and frequency of radio-frequency signals using the Morlet transform is presented. The theoretical analysis and simulation results show that the method is suitable for detecting phase jitter, phase discontinuities, and frequency contents in telecommunication signals.
{"title":"Measurement of phase and frequency variations in radio-frequency signals","authors":"M. Soma, W. Haileselassie, Jessica Sherrid","doi":"10.1109/VTEST.2003.1197652","DOIUrl":"https://doi.org/10.1109/VTEST.2003.1197652","url":null,"abstract":"A method to measure time-varying phase and frequency of radio-frequency signals using the Morlet transform is presented. The theoretical analysis and simulation results show that the method is suitable for detecting phase jitter, phase discontinuities, and frequency contents in telecommunication signals.","PeriodicalId":292996,"journal":{"name":"Proceedings. 21st VLSI Test Symposium, 2003.","volume":"141 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124492033","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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