{"title":"Deriving process networks from weakly dynamic applications in system-level design","authors":"T. Stefanov, E. Deprettere","doi":"10.1145/944645.944673","DOIUrl":null,"url":null,"abstract":"We present an approach to the automatic derivation of executable process network specifications from weakly dynamic applications. We introduce the notions of dynamic single assignment code, approximated dependence graph, and linearly bounded sets to model and capture weakly dynamic (data-dependent) behavior of applications at the task-level of abstraction. Process networks are simple parallel processing models that match the emerging multiprocessor architectures in the sense that the mapping of process network specifications of applications onto multiprocessor architectures can be done in a systematic and transparent way.","PeriodicalId":174422,"journal":{"name":"First IEEE/ACM/IFIP International Conference on Hardware/ Software Codesign and Systems Synthesis (IEEE Cat. No.03TH8721)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2003-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"30","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"First IEEE/ACM/IFIP International Conference on Hardware/ Software Codesign and Systems Synthesis (IEEE Cat. No.03TH8721)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/944645.944673","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 30
Abstract
We present an approach to the automatic derivation of executable process network specifications from weakly dynamic applications. We introduce the notions of dynamic single assignment code, approximated dependence graph, and linearly bounded sets to model and capture weakly dynamic (data-dependent) behavior of applications at the task-level of abstraction. Process networks are simple parallel processing models that match the emerging multiprocessor architectures in the sense that the mapping of process network specifications of applications onto multiprocessor architectures can be done in a systematic and transparent way.