Hardware/software cosimulation is the key process to shorten the design turn around time. We have proposed a novel technique, called virtual synchronization, for fast and time accurate cosimulation that involves interacting component simulators. We further extend the virtual synchronization technique with OS modeling for the case where multiple software tasks are executed under the supervision of a real-time operating system. The OS modeler models the RTOS overheads of context switching and tick interrupt handling as well as preemption behavior. While maintaining the timing accuracy to an acceptable level below a few percent, we could reduce the simulation time drastically compared with existing conservative approach by removing the need of time synchronization between simulators. It is confirmed with a preliminary experiment with a multimedia example that consists of four real-life tasks.
{"title":"Virtual synchronization technique with OS modeling for fast and time-accurate cosimulation","authors":"Youngmin Yi, Dohyung Kim, S. Ha","doi":"10.1145/944645.944647","DOIUrl":"https://doi.org/10.1145/944645.944647","url":null,"abstract":"Hardware/software cosimulation is the key process to shorten the design turn around time. We have proposed a novel technique, called virtual synchronization, for fast and time accurate cosimulation that involves interacting component simulators. We further extend the virtual synchronization technique with OS modeling for the case where multiple software tasks are executed under the supervision of a real-time operating system. The OS modeler models the RTOS overheads of context switching and tick interrupt handling as well as preemption behavior. While maintaining the timing accuracy to an acceptable level below a few percent, we could reduce the simulation time drastically compared with existing conservative approach by removing the need of time synchronization between simulators. It is confirmed with a preliminary experiment with a multimedia example that consists of four real-life tasks.","PeriodicalId":174422,"journal":{"name":"First IEEE/ACM/IFIP International Conference on Hardware/ Software Codesign and Systems Synthesis (IEEE Cat. No.03TH8721)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121122007","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The semiconductor industry is experiencing a paradigm shift from "computation-bound design" to "communication-bound design": the number of transistors that can be reached in a clock cycle, and not those that can be integrated on a chip, will drive the design process. Interconnect latency will have a major impact on the design of on-chip communication architectures, which increasingly rely on wire pipelining to go beyond the capabilities of traditional wire buffering. The insertion of stateful repeaters on long wires, instead of simply stateless repeaters, carries major sequences for the synchronous design methodology. This is the foundation of the design flows for the majority of commercial chips today, but, if left unchanged, will lead to an exacerbation of the timing closure problem for tomorrow's design flows. New methodologies that regard the chip as a distributed system are necessary. Latency-insensitive design is a step in this direction.
{"title":"On-chip communication design: roadblocks and avenues","authors":"L. Carloni, A. Sangiovanni-Vincentelli","doi":"10.1145/944645.944666","DOIUrl":"https://doi.org/10.1145/944645.944666","url":null,"abstract":"The semiconductor industry is experiencing a paradigm shift from \"computation-bound design\" to \"communication-bound design\": the number of transistors that can be reached in a clock cycle, and not those that can be integrated on a chip, will drive the design process. Interconnect latency will have a major impact on the design of on-chip communication architectures, which increasingly rely on wire pipelining to go beyond the capabilities of traditional wire buffering. The insertion of stateful repeaters on long wires, instead of simply stateless repeaters, carries major sequences for the synchronous design methodology. This is the foundation of the design flows for the majority of commercial chips today, but, if left unchanged, will lead to an exacerbation of the timing closure problem for tomorrow's design flows. New methodologies that regard the chip as a distributed system are necessary. Latency-insensitive design is a step in this direction.","PeriodicalId":174422,"journal":{"name":"First IEEE/ACM/IFIP International Conference on Hardware/ Software Codesign and Systems Synthesis (IEEE Cat. No.03TH8721)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127221578","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a correct-by-construction synthesis method for generating operating system based device drivers from a formally specified device behavior model. Existing driver development is largely manual using an ad-hoc design methodology. Consequently, this task is error prone and becomes a bottleneck in embedded system design methodology. Our solution to this problem starts by accurately specifying device access behavior with a formal model, viz. extended event driven finite state machines. We state easy check soundness conditions on the model that subsequently guarantee properties such as bounded execution time and deadlock-free behavior. We design a deadlock-free resource accessing scheme for our device access model. Finally, we synthesize an operating system (OS) based event processing mechanism, which is the core of the device driver, using a disciplined methodology that assures the correctness of the resulting driver. We validate our synthesis method using two case studies: an infrared port and the USB device controller for an SA1100 based handheld. Besides assuring a correct-by-construction driver, the size of the specification is 70% smaller than a manually written driver, which is a strong indicator of improved design productivity.
{"title":"Synthesizing operating system based device drivers in embedded systems","authors":"Shaojie Wang, S. Malik","doi":"10.1145/944645.944655","DOIUrl":"https://doi.org/10.1145/944645.944655","url":null,"abstract":"This paper presents a correct-by-construction synthesis method for generating operating system based device drivers from a formally specified device behavior model. Existing driver development is largely manual using an ad-hoc design methodology. Consequently, this task is error prone and becomes a bottleneck in embedded system design methodology. Our solution to this problem starts by accurately specifying device access behavior with a formal model, viz. extended event driven finite state machines. We state easy check soundness conditions on the model that subsequently guarantee properties such as bounded execution time and deadlock-free behavior. We design a deadlock-free resource accessing scheme for our device access model. Finally, we synthesize an operating system (OS) based event processing mechanism, which is the core of the device driver, using a disciplined methodology that assures the correctness of the resulting driver. We validate our synthesis method using two case studies: an infrared port and the USB device controller for an SA1100 based handheld. Besides assuring a correct-by-construction driver, the size of the specification is 70% smaller than a manually written driver, which is a strong indicator of improved design productivity.","PeriodicalId":174422,"journal":{"name":"First IEEE/ACM/IFIP International Conference on Hardware/ Software Codesign and Systems Synthesis (IEEE Cat. No.03TH8721)","volume":"222 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122399418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
B. Mohebbi, Eliseu Chavez Filho, R. Maestre, Mark Davies, F. Kurdahi
We present a case study involving the implementation of a complete Wideband CDMA (WCDMA) digital receiver part of an AMR channel onto a reconfigurable core. WCDMA is one of the two major standards for the third generation (3G) cellular systems. Traditionally most of the receiver components were confined to ASIC implementation for performance, size and power consumption reasons. The MS1 reconfigurable DSP core provides both a microprocessor and reconfigurable fabric as well as a variety of peripherals. The various functions of the receiver were mapped onto different core components. The complete system was tested both in simulation as well as on a hardware platform comprising a silicon implementation of the MS1 DSP core.
{"title":"A case study of mapping a software-defined radio (SDR) application on a reconfigurable DSP core","authors":"B. Mohebbi, Eliseu Chavez Filho, R. Maestre, Mark Davies, F. Kurdahi","doi":"10.1145/944645.944676","DOIUrl":"https://doi.org/10.1145/944645.944676","url":null,"abstract":"We present a case study involving the implementation of a complete Wideband CDMA (WCDMA) digital receiver part of an AMR channel onto a reconfigurable core. WCDMA is one of the two major standards for the third generation (3G) cellular systems. Traditionally most of the receiver components were confined to ASIC implementation for performance, size and power consumption reasons. The MS1 reconfigurable DSP core provides both a microprocessor and reconfigurable fabric as well as a variety of peripherals. The various functions of the receiver were mapped onto different core components. The complete system was tested both in simulation as well as on a hardware platform comprising a silicon implementation of the MS1 DSP core.","PeriodicalId":174422,"journal":{"name":"First IEEE/ACM/IFIP International Conference on Hardware/ Software Codesign and Systems Synthesis (IEEE Cat. No.03TH8721)","volume":"372 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122855059","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. Bergamaschi, G. Martin, W. Wolf, R. Ernst, K. Vissers, J. Kouloheris
Over the last 15 years we have seen and helped the evolution of design from behavioral modeling to hardware/software co-design, to today's system-level design. Arguably, many of the research efforts on behavioral synthesis, hardware / software co-design, co-simulation etc. have made their way into successful commercial tools, while others went no further than a conference paper. As we continue and expand system-level research with new approaches opening exciting new research avenues, we have an obligation to look back at our successes and failures. Then looking towards the future, we must answer the question: are we solving the right problems with the right solutions at the right time, or should we go back to the drawing board and think of brand new research approaches.This panel will bring together panelists experienced in various aspects of system-level design who will present different views on what this community has achieved over the last 15 years and draw a roadmap for future research.
{"title":"The future of system-level design: can we find the right solutions to the right problems at the right time?","authors":"R. Bergamaschi, G. Martin, W. Wolf, R. Ernst, K. Vissers, J. Kouloheris","doi":"10.1145/944645.944704","DOIUrl":"https://doi.org/10.1145/944645.944704","url":null,"abstract":"Over the last 15 years we have seen and helped the evolution of design from behavioral modeling to hardware/software co-design, to today's system-level design. Arguably, many of the research efforts on behavioral synthesis, hardware / software co-design, co-simulation etc. have made their way into successful commercial tools, while others went no further than a conference paper. As we continue and expand system-level research with new approaches opening exciting new research avenues, we have an obligation to look back at our successes and failures. Then looking towards the future, we must answer the question: are we solving the right problems with the right solutions at the right time, or should we go back to the drawing board and think of brand new research approaches.This panel will bring together panelists experienced in various aspects of system-level design who will present different views on what this community has achieved over the last 15 years and draw a roadmap for future research.","PeriodicalId":174422,"journal":{"name":"First IEEE/ACM/IFIP International Conference on Hardware/ Software Codesign and Systems Synthesis (IEEE Cat. No.03TH8721)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128326630","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This panel will bring together members who are responsible for leading research directions in embedded systems, Systems-on-Chip (SOCs), and the attendant software and hardware, through their roles in funding research, coordinating industrial consortia, chairing professional societies, and building a community of systems researchers. The panelists will share their views on research challenges in systems, opportunities for research funding, and the role of academics, tool vendors, industry, and consortia in solving challenges for the design and development of next generation embedded systems.
{"title":"Driving agenda for systems research","authors":"N. Dutt, J. Sztipanovits, Masaki Hirata","doi":"10.1145/944645.944670","DOIUrl":"https://doi.org/10.1145/944645.944670","url":null,"abstract":"This panel will bring together members who are responsible for leading research directions in embedded systems, Systems-on-Chip (SOCs), and the attendant software and hardware, through their roles in funding research, coordinating industrial consortia, chairing professional societies, and building a community of systems researchers. The panelists will share their views on research challenges in systems, opportunities for research funding, and the role of academics, tool vendors, industry, and consortia in solving challenges for the design and development of next generation embedded systems.","PeriodicalId":174422,"journal":{"name":"First IEEE/ACM/IFIP International Conference on Hardware/ Software Codesign and Systems Synthesis (IEEE Cat. No.03TH8721)","volume":"179 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128529459","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Summary form only given. The article describes a state-centric abstraction for application users to interact with sensor networks. Just as in data-centric routing and storage where physical nodes are less important than the data itself, state-centric abstraction introduces "states" as a natural vocabulary to describe spatio-temporal physical phenomena that the sensor networks are typically designed for. Application programmers specify the computation as creation, sharing and transformation of states, which naturally map to descriptions in signal processing and control applications. We argue that due to the dynamic nature of sensor networks, programs written in state-centric abstractions are more invariant to constant changes in data stream configurations and make the resulting software more portable across multiple sensor network platforms. With the help of models of sensor collaboration, sensing and estimation, the state-centric specifications are mapped into collaborative processing tasks at compile time, and further maintained at run time, leveraging the data-centric caching and routing services. We use a multi-target tracking system as an example to show how state-centric programming models can raise the abstraction level for users to interact with sensor networks and help modularize the design.
{"title":"Programming embedded networked sensor systems","authors":"F. Zhao, Jie Liu, J. Reich, M. Chu, Juan Liu","doi":"10.1145/944645.944657","DOIUrl":"https://doi.org/10.1145/944645.944657","url":null,"abstract":"Summary form only given. The article describes a state-centric abstraction for application users to interact with sensor networks. Just as in data-centric routing and storage where physical nodes are less important than the data itself, state-centric abstraction introduces \"states\" as a natural vocabulary to describe spatio-temporal physical phenomena that the sensor networks are typically designed for. Application programmers specify the computation as creation, sharing and transformation of states, which naturally map to descriptions in signal processing and control applications. We argue that due to the dynamic nature of sensor networks, programs written in state-centric abstractions are more invariant to constant changes in data stream configurations and make the resulting software more portable across multiple sensor network platforms. With the help of models of sensor collaboration, sensing and estimation, the state-centric specifications are mapped into collaborative processing tasks at compile time, and further maintained at run time, leveraging the data-centric caching and routing services. We use a multi-target tracking system as an example to show how state-centric programming models can raise the abstraction level for users to interact with sensor networks and help modularize the design.","PeriodicalId":174422,"journal":{"name":"First IEEE/ACM/IFIP International Conference on Hardware/ Software Codesign and Systems Synthesis (IEEE Cat. No.03TH8721)","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129440828","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We present an approach to the automatic derivation of executable process network specifications from weakly dynamic applications. We introduce the notions of dynamic single assignment code, approximated dependence graph, and linearly bounded sets to model and capture weakly dynamic (data-dependent) behavior of applications at the task-level of abstraction. Process networks are simple parallel processing models that match the emerging multiprocessor architectures in the sense that the mapping of process network specifications of applications onto multiprocessor architectures can be done in a systematic and transparent way.
{"title":"Deriving process networks from weakly dynamic applications in system-level design","authors":"T. Stefanov, E. Deprettere","doi":"10.1145/944645.944673","DOIUrl":"https://doi.org/10.1145/944645.944673","url":null,"abstract":"We present an approach to the automatic derivation of executable process network specifications from weakly dynamic applications. We introduce the notions of dynamic single assignment code, approximated dependence graph, and linearly bounded sets to model and capture weakly dynamic (data-dependent) behavior of applications at the task-level of abstraction. Process networks are simple parallel processing models that match the emerging multiprocessor architectures in the sense that the mapping of process network specifications of applications onto multiprocessor architectures can be done in a systematic and transparent way.","PeriodicalId":174422,"journal":{"name":"First IEEE/ACM/IFIP International Conference on Hardware/ Software Codesign and Systems Synthesis (IEEE Cat. No.03TH8721)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114867908","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. Bergamaschi, Youngsoo Shin, N. Dhanwada, S. Bhattacharya, W. Dougherty, I. Nair, J. Darringer, S. Paliwal
Systems-on-chip (SoC) continue to be very complex to design and verify, despite extensive component reuse. Although reusable components are predesigned and preverified, when they are assembled in an SoC there is no guarantee that the whole system will behave as expected from a performance, cost and integration point of view. In many cases this is because of faulty early design decisions regarding the architecture, core selection, floorplanning, etc. This paper presents a system for early analysis of SoCs which helps designers make early decisions regarding performance, area, timing and power; and allows them to quickly evaluate cross-domain effects, such as the effect that an architectural decision may have on the performance and chip area.
{"title":"SEAS: a system for early analysis of SoCs","authors":"R. Bergamaschi, Youngsoo Shin, N. Dhanwada, S. Bhattacharya, W. Dougherty, I. Nair, J. Darringer, S. Paliwal","doi":"10.1145/944645.944687","DOIUrl":"https://doi.org/10.1145/944645.944687","url":null,"abstract":"Systems-on-chip (SoC) continue to be very complex to design and verify, despite extensive component reuse. Although reusable components are predesigned and preverified, when they are assembled in an SoC there is no guarantee that the whole system will behave as expected from a performance, cost and integration point of view. In many cases this is because of faulty early design decisions regarding the architecture, core selection, floorplanning, etc. This paper presents a system for early analysis of SoCs which helps designers make early decisions regarding performance, area, timing and power; and allows them to quickly evaluate cross-domain effects, such as the effect that an architectural decision may have on the performance and chip area.","PeriodicalId":174422,"journal":{"name":"First IEEE/ACM/IFIP International Conference on Hardware/ Software Codesign and Systems Synthesis (IEEE Cat. No.03TH8721)","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117307738","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
One of the most challenging problems in high-level synthesis is how to quickly explore a wide range of design options to achieve high-quality designs. This paper presents an Integrated Framework for Design Optimization and Space Minimization (IDOM) towards finding the minimum configuration satisfying timing and code size constraints. We show an effective way to reduce the design space to be explored through the study of the fundamental properties and relations among multiple design parameters, such as retiming value, unfolding factor, timing, and code size. Theories are presented to produce a small set of feasible design choices with provable quality. IDOM algorithm is proposed to generate high-quality design by integrating performance and code size optimization techniques. The experimental results on a set of DSP benchmarks show the efficiency and effectiveness of the IDOM algorithm. It constantly generates the minimal configuration for all the benchmarks. The cost of design space exploration using IDOM is only 3% of that using the standard method.
{"title":"Design space minimization with timing and code size optimization for embedded DSP","authors":"Qingfeng Zhuge, Z. Shao, Bin Xiao, E. Sha","doi":"10.1145/944645.944685","DOIUrl":"https://doi.org/10.1145/944645.944685","url":null,"abstract":"One of the most challenging problems in high-level synthesis is how to quickly explore a wide range of design options to achieve high-quality designs. This paper presents an Integrated Framework for Design Optimization and Space Minimization (IDOM) towards finding the minimum configuration satisfying timing and code size constraints. We show an effective way to reduce the design space to be explored through the study of the fundamental properties and relations among multiple design parameters, such as retiming value, unfolding factor, timing, and code size. Theories are presented to produce a small set of feasible design choices with provable quality. IDOM algorithm is proposed to generate high-quality design by integrating performance and code size optimization techniques. The experimental results on a set of DSP benchmarks show the efficiency and effectiveness of the IDOM algorithm. It constantly generates the minimal configuration for all the benchmarks. The cost of design space exploration using IDOM is only 3% of that using the standard method.","PeriodicalId":174422,"journal":{"name":"First IEEE/ACM/IFIP International Conference on Hardware/ Software Codesign and Systems Synthesis (IEEE Cat. No.03TH8721)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123639979","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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