A data simulator for performance monitoring of vlsi ethernet hardware

R. Whitty, D. Girma
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引用次数: 1

Abstract

The paper describes the design and operation of a microprocessor-based direct memory access data simulator for monitoring the performance of an Ethernet node. The node hardware is based on recently available special-purpose VLSI devices and has been designed to permit the transmission of packetised data and speech at a rate of 10 Mbits/s. An example of the benefit of using such a design tool in time-critical applications is given. It is concluded that such a simulator is an important development aid in the design of low-cost Ethernet hardware.
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一个用于监控超大规模以太网硬件性能的数据模拟器
本文介绍了一种基于微处理器的直接存储器访问数据模拟器的设计与实现,用于监控以太网节点的性能。该节点硬件基于最近可用的专用VLSI设备,并被设计为允许以10 mbit /s的速率传输分组数据和语音。给出了在时间要求严格的应用中使用这种设计工具的好处的一个例子。该仿真器是低成本以太网硬件设计的重要发展辅助工具。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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Simulating hardware structures in occam Techniques for developing and testing microprocessor systems Design considerations for a single-chip fault tolerant VLSI microprocessor The development of fault tolerant computer systems using dual processing techniques Fault tolerance and self-checking techniques in microprocessor-based system design
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