Testing microprocessor systems at the development stage can take up to a third of the total development time and yet techniques for testing may only be thought about once the design stage has been undertaken. A correct approach to testing can considerably reduce the time needed to take a prototype through to a working system, and this not only means that a product can be on the market faster, but the development costs can be considerably reduced. The paper looks at the techniques and requirements for testing microprocessor-based systems and suggests alternatives to expensive development systems.
{"title":"Techniques for developing and testing microprocessor systems","authors":"C. Hudson","doi":"10.1049/sm.1985.0022","DOIUrl":"https://doi.org/10.1049/sm.1985.0022","url":null,"abstract":"Testing microprocessor systems at the development stage can take up to a third of the total development time and yet techniques for testing may only be thought about once the design stage has been undertaken. A correct approach to testing can considerably reduce the time needed to take a prototype through to a working system, and this not only means that a product can be on the market faster, but the development costs can be considerably reduced. The paper looks at the techniques and requirements for testing microprocessor-based systems and suggests alternatives to expensive development systems.","PeriodicalId":246116,"journal":{"name":"Softw. Microsystems","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1985-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124877643","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Occam is a low-level programming language designed specifically to program an array of transputers, although it may be implemented on a single transputer or other processor using a suitable run-time support system. The paper describes the use of occam to model combinatorial and sequential logic systems. The suitability of occam for such modelling is discussed.
{"title":"Simulating hardware structures in occam","authors":"R. Dowsing","doi":"10.1049/sm.1985.0021","DOIUrl":"https://doi.org/10.1049/sm.1985.0021","url":null,"abstract":"Occam is a low-level programming language designed specifically to program an array of transputers, although it may be implemented on a single transputer or other processor using a suitable run-time support system. The paper describes the use of occam to model combinatorial and sequential logic systems. The suitability of occam for such modelling is discussed.","PeriodicalId":246116,"journal":{"name":"Softw. Microsystems","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1985-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116029850","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A design approach is presented for a general-purpose VLSI fault tolerant microprocessor, with redundancy designed into the internal chip architecture. The design features are internal automatic state storage and rollback/retry mechanism and a microprogrammed ALU design. The reliability of the design is estimated using a system model of reliability behaviour, and is compared with that of other fault tolerant design strategies. Finally, the effect of the fault tolerance on processor performance is discussed.
{"title":"Design considerations for a single-chip fault tolerant VLSI microprocessor","authors":"A. Goode","doi":"10.1049/sm.1985.0016","DOIUrl":"https://doi.org/10.1049/sm.1985.0016","url":null,"abstract":"A design approach is presented for a general-purpose VLSI fault tolerant microprocessor, with redundancy designed into the internal chip architecture. The design features are internal automatic state storage and rollback/retry mechanism and a microprogrammed ALU design. The reliability of the design is estimated using a system model of reliability behaviour, and is compared with that of other fault tolerant design strategies. Finally, the effect of the fault tolerance on processor performance is discussed.","PeriodicalId":246116,"journal":{"name":"Softw. Microsystems","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1985-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121091068","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Transient disturbances to microprocessor systems can cause program execution to depart from its normal sequence of operations. In the paper figures for the probability of recovery following a transient disturbance are calculated. The approach is based on analysis of program execution following a random jump to an arbitrary address within the memory map, and comparative figures are presented for a number of microprocessors. Suggestions are made for enhancing the probability of recovery.
{"title":"Erroneous execution and recovery in microprocessor systems","authors":"R. G. Halse, C. Preece","doi":"10.1049/sm.1985.0018","DOIUrl":"https://doi.org/10.1049/sm.1985.0018","url":null,"abstract":"Transient disturbances to microprocessor systems can cause program execution to depart from its normal sequence of operations. In the paper figures for the probability of recovery following a transient disturbance are calculated. The approach is based on analysis of program execution following a random jump to an arbitrary address within the memory map, and comparative figures are presented for a number of microprocessors. Suggestions are made for enhancing the probability of recovery.","PeriodicalId":246116,"journal":{"name":"Softw. Microsystems","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1985-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133657477","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The paper discusses ways of building a dual processed computer system to provide a highly reliable fault tolerant configuration. The need and justification for fault tolerant systems is discussed and the comparative availability that can be expected from single and dual configurations is calculated. Based on systems implemented by CAP, two of the most important types of dual processing systems are discussed: namely load sharing and continuous processing systems. The load sharing approach to fault tolerance is particularly important for transaction processing applications because it offers the opportunity to build a fault tolerant system for a cost close to that of a conventional single-computer system. An example based on CAP's system for the Durham Constabulary on Perkin-Elmer equipment is discussed. The continuous processing system described is based on CAPTEC, CAFs operating system for Digital Equipment Corporation computers, which provides a continuous processing system where the system continues uninterrupted on a single failure.
{"title":"The development of fault tolerant computer systems using dual processing techniques","authors":"P. J. Russell","doi":"10.1049/sm.1985.0019","DOIUrl":"https://doi.org/10.1049/sm.1985.0019","url":null,"abstract":"The paper discusses ways of building a dual processed computer system to provide a highly reliable fault tolerant configuration. The need and justification for fault tolerant systems is discussed and the comparative availability that can be expected from single and dual configurations is calculated. Based on systems implemented by CAP, two of the most important types of dual processing systems are discussed: namely load sharing and continuous processing systems. The load sharing approach to fault tolerance is particularly important for transaction processing applications because it offers the opportunity to build a fault tolerant system for a cost close to that of a conventional single-computer system. An example based on CAP's system for the Durham Constabulary on Perkin-Elmer equipment is discussed. The continuous processing system described is based on CAPTEC, CAFs operating system for Digital Equipment Corporation computers, which provides a continuous processing system where the system continues uninterrupted on a single failure.","PeriodicalId":246116,"journal":{"name":"Softw. Microsystems","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1985-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121964553","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Fault tolerant design is receiving considerable attention at present in order to safeguard against improper operation of digital systems in critical applications. A number of multiprocessor systems featuring hardware fault tolerance are now available commercially. The paper presents an overview of some of the work done so far in the application of fault tolerance techniques to improve the reliability and availability of microprocessor-based systems. An alternative approach to enhance the reliability of a system is to apply self-checking techniques, primarily through the use of error detecting codes. By merging the fault tolerance and the self-checking techniques, the reliability and the maintainability of microprocessor-based systems can be significantly improved.
{"title":"Fault tolerance and self-checking techniques in microprocessor-based system design","authors":"P. Lala","doi":"10.1049/sm.1985.0015","DOIUrl":"https://doi.org/10.1049/sm.1985.0015","url":null,"abstract":"Fault tolerant design is receiving considerable attention at present in order to safeguard against improper operation of digital systems in critical applications. A number of multiprocessor systems featuring hardware fault tolerance are now available commercially. The paper presents an overview of some of the work done so far in the application of fault tolerance techniques to improve the reliability and availability of microprocessor-based systems. An alternative approach to enhance the reliability of a system is to apply self-checking techniques, primarily through the use of error detecting codes. By merging the fault tolerance and the self-checking techniques, the reliability and the maintainability of microprocessor-based systems can be significantly improved.","PeriodicalId":246116,"journal":{"name":"Softw. Microsystems","volume":"04 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1985-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129711368","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A circuit based on the AM2901 bit slice processor and a serial/parallel multiplier is described along with the algorithm to compute the base-2 DIF fast Fourier transform.
{"title":"A microprogrammable peripheral unit and the FFT","authors":"A. Yong, M. Juanatey","doi":"10.1049/sm.1985.0010","DOIUrl":"https://doi.org/10.1049/sm.1985.0010","url":null,"abstract":"A circuit based on the AM2901 bit slice processor and a serial/parallel multiplier is described along with the algorithm to compute the base-2 DIF fast Fourier transform.","PeriodicalId":246116,"journal":{"name":"Softw. Microsystems","volume":"134 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1985-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133734439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The paper presents a new approach to fault diagnosis of stored program controlled (SPC) switching systems. It uses the functional behaviour of SPC systems to model faults. This method uses circuit, structure descriptions and call processing programs to generate automatically the data required for fault analysis and avoids fault simulation.
{"title":"Fault diagnosis of SPC switching systems based on structure and signalling","authors":"C. Shashidhar, F. Coakley","doi":"10.1049/sm.1985.0009","DOIUrl":"https://doi.org/10.1049/sm.1985.0009","url":null,"abstract":"The paper presents a new approach to fault diagnosis of stored program controlled (SPC) switching systems. It uses the functional behaviour of SPC systems to model faults. This method uses circuit, structure descriptions and call processing programs to generate automatically the data required for fault analysis and avoids fault simulation.","PeriodicalId":246116,"journal":{"name":"Softw. Microsystems","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1985-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116341227","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The need is argued for a rigorous and general theory of structured programming as a basis for improving software quality. Formal graph theoretic methods are developed which allow the structural modelling, metrication and reconstruction of sequential programs in terms of precisely defined general sets of basic control structures. Throughout, concepts are illustrated by examples based on actual Basic and Pascal text.
{"title":"A rigorous approach to structural analysis and metrication of software","authors":"R. Whitty, N. Fenton, A. Kaposi","doi":"10.1049/sm.1985.0002","DOIUrl":"https://doi.org/10.1049/sm.1985.0002","url":null,"abstract":"The need is argued for a rigorous and general theory of structured programming as a basis for improving software quality. Formal graph theoretic methods are developed which allow the structural modelling, metrication and reconstruction of sequential programs in terms of precisely defined general sets of basic control structures. Throughout, concepts are illustrated by examples based on actual Basic and Pascal text.","PeriodicalId":246116,"journal":{"name":"Softw. Microsystems","volume":"104 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1985-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127651327","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The paper describes the design and operation of a microprocessor-based direct memory access data simulator for monitoring the performance of an Ethernet node. The node hardware is based on recently available special-purpose VLSI devices and has been designed to permit the transmission of packetised data and speech at a rate of 10 Mbits/s. An example of the benefit of using such a design tool in time-critical applications is given. It is concluded that such a simulator is an important development aid in the design of low-cost Ethernet hardware.
{"title":"A data simulator for performance monitoring of vlsi ethernet hardware","authors":"R. Whitty, D. Girma","doi":"10.1049/SM:19850003","DOIUrl":"https://doi.org/10.1049/SM:19850003","url":null,"abstract":"The paper describes the design and operation of a microprocessor-based direct memory access data simulator for monitoring the performance of an Ethernet node. The node hardware is based on recently available special-purpose VLSI devices and has been designed to permit the transmission of packetised data and speech at a rate of 10 Mbits/s. An example of the benefit of using such a design tool in time-critical applications is given. It is concluded that such a simulator is an important development aid in the design of low-cost Ethernet hardware.","PeriodicalId":246116,"journal":{"name":"Softw. Microsystems","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1985-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114868535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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