Data-rate-aware FPGA-based acceleration framework for streaming applications

Abstract

In heterogeneous architectures, FPGAs are not only expected to provide higher performance, but also to provide a more energy efficient solution for computationally intensive tasks. While parallelism and pipelining enhance performance on FPGA platforms, the data transfer rate from/to off-chip memory can cause performance degradation. We propose an automated high-level synthesis framework for FPGA-based acceleration of nested loops on large multidimensional input data sets. Given the high-level of parallelism in such applications, our proposed data prefetching algorithm determines the data rate for each parallel datapath. The empirical results on a case study in scientific computing show that FPGA mapping of such nested loops accelerates the application compared to traditional mapping on multicores. The FPGA-accelerated computation results in 3x speedup in runtime and 27x energy-delay-product savings compared to multicore computation.