Optimal processor interface for CGRA-based accelerators implemented on FPGAs

L. Jung, C. Hochberger
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引用次数: 2

Abstract

Coarse Grained Reconfigurable Arrays (CGRA) can be used to substantially boost the processing power of embedded applications. They can be included in typical system-on-chip architectures to execute computationally demanding parts of the application. Delegating execution to the CGRA requires the exchange of live in/out variables between the processor core and the CGRA. In this paper we search the optimal interface between the surrounding system and the CGRA with respect to impact on the operating frequency, the used resources and the runtime overhead.
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fpga上实现基于cgra的加速器的最优处理器接口
粗粒度可重构阵列(CGRA)可用于大幅提高嵌入式应用程序的处理能力。它们可以包含在典型的片上系统架构中,以执行应用程序中计算要求很高的部分。将执行委托给CGRA需要在处理器核心和CGRA之间交换活的in/out变量。本文从对运行频率、资源使用和运行时开销的影响等方面研究了周边系统与CGRA之间的最优接口。
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