{"title":"Synchronous Rectifier Design Considerations for Solid-State Transformer Light-Load Stability","authors":"O. Yu, Chih-Shen Yeh, J. Lai","doi":"10.1109/ACEPT.2018.8610790","DOIUrl":null,"url":null,"abstract":"Increasing usage of high output voltage, low output current resonant-based DC-DC converter systems can face a stability issue when cycle-by-cycle drain-source synchronous rectification (SR) controllers are paired with low RDS, on rectifier switches. A current resonance phenomenon can be observed at low power conditions within the LLC resonant converter. This instability can lead to inconsistent SR operation, excessive conduction loss, output ripple, and poor light-load efficiency. In this paper, the issue is root caused, simulated, and an FPGAbased duty cycle rate limiter is built and tested to verify a possible method of alleviating the issue.","PeriodicalId":296432,"journal":{"name":"2018 Asian Conference on Energy, Power and Transportation Electrification (ACEPT)","volume":"86 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 Asian Conference on Energy, Power and Transportation Electrification (ACEPT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ACEPT.2018.8610790","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
Increasing usage of high output voltage, low output current resonant-based DC-DC converter systems can face a stability issue when cycle-by-cycle drain-source synchronous rectification (SR) controllers are paired with low RDS, on rectifier switches. A current resonance phenomenon can be observed at low power conditions within the LLC resonant converter. This instability can lead to inconsistent SR operation, excessive conduction loss, output ripple, and poor light-load efficiency. In this paper, the issue is root caused, simulated, and an FPGAbased duty cycle rate limiter is built and tested to verify a possible method of alleviating the issue.
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