SIESTA: a multi-facet scan design system

Abstract

Scan design methodology has led to a range of design-for-testability techniques. However, scan techniques are not universally accepted by circuit designers because of the various overheads involved, such as chip area, performance, I/O pin count and test application time. The authors present a multi-facet scan design system called SIESTA that attempts to find solutions that satisfy designer goals and constraints. SIESTA incorporates a range of methodologies and optimization techniques that deal with the issues of partial scan, circuit partitioning, test application and scan path chaining. It employs several new concepts that do not exist in other scan design systems.<>