Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246236
S. Narayanan, C. Njinda, Rajesh K. Gupta, M. Breuer
Scan design methodology has led to a range of design-for-testability techniques. However, scan techniques are not universally accepted by circuit designers because of the various overheads involved, such as chip area, performance, I/O pin count and test application time. The authors present a multi-facet scan design system called SIESTA that attempts to find solutions that satisfy designer goals and constraints. SIESTA incorporates a range of methodologies and optimization techniques that deal with the issues of partial scan, circuit partitioning, test application and scan path chaining. It employs several new concepts that do not exist in other scan design systems.<>
{"title":"SIESTA: a multi-facet scan design system","authors":"S. Narayanan, C. Njinda, Rajesh K. Gupta, M. Breuer","doi":"10.1109/EURDAC.1992.246236","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246236","url":null,"abstract":"Scan design methodology has led to a range of design-for-testability techniques. However, scan techniques are not universally accepted by circuit designers because of the various overheads involved, such as chip area, performance, I/O pin count and test application time. The authors present a multi-facet scan design system called SIESTA that attempts to find solutions that satisfy designer goals and constraints. SIESTA incorporates a range of methodologies and optimization techniques that deal with the issues of partial scan, circuit partitioning, test application and scan path chaining. It employs several new concepts that do not exist in other scan design systems.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114905686","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246203
G. Scholz, W. Wilkes
An information model for a folded design description which corresponds to electronic design interchange format (EDIF) version 2.0.0, using the language Express, is presented. It is shown that it can be easily extended to a model for an unfolded description. A method to compute the actual values for occurrences of views, nets, and ports, is given, which is based on the back-annotation facilities of EDIF and may help to uncover EDIF's underlying semantics.<>
{"title":"Information modelling of folded and unfolded design","authors":"G. Scholz, W. Wilkes","doi":"10.1109/EURDAC.1992.246203","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246203","url":null,"abstract":"An information model for a folded design description which corresponds to electronic design interchange format (EDIF) version 2.0.0, using the language Express, is presented. It is shown that it can be easily extended to a model for an unfolded description. A method to compute the actual values for occurrences of views, nets, and ports, is given, which is based on the back-annotation facilities of EDIF and may help to uncover EDIF's underlying semantics.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114954390","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246210
J. Roychowdhury, A. Newton, D. Pederson
A new technique, based on convolution, has been developed for the time domain simulation of uniform RC lines. This technique is exact, requiring no simplification of the line's internal mechanism. It is shown that though the impulse responses of uniform RC lines are ill-behaved and unsuitable for direct numerical implementation, the use of a convolutional formula obtained by generalizing the trapezoidal integration method leads to well-behaved analytic forms that can be directly implemented. The new technique makes no approximation to the uniform distribution of resistance and capacitance. Experimental results using industrial IC interconnect demonstrate the efficacy of the new technique.<>
{"title":"An exact analytic technique for simulating uniform RC lines","authors":"J. Roychowdhury, A. Newton, D. Pederson","doi":"10.1109/EURDAC.1992.246210","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246210","url":null,"abstract":"A new technique, based on convolution, has been developed for the time domain simulation of uniform RC lines. This technique is exact, requiring no simplification of the line's internal mechanism. It is shown that though the impulse responses of uniform RC lines are ill-behaved and unsuitable for direct numerical implementation, the use of a convolutional formula obtained by generalizing the trapezoidal integration method leads to well-behaved analytic forms that can be directly implemented. The new technique makes no approximation to the uniform distribution of resistance and capacitance. Experimental results using industrial IC interconnect demonstrate the efficacy of the new technique.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114297757","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246237
K. Müller-Glaser, J. Bortolazzi, Y. Tanurhan
The authors provide an overview of techniques for the specification of complex, heterogeneous systems, i.e. microsystems or automotive control systems including hardware (analog and digital electronics, mechanical or optical actuators and sensors) and software. An approach to an integrated environment to support and control the requirement definition, specification and system design phases is described. This approach combines behavioral, functional, and data-oriented specifications based on formal languages, as well as knowledge-based concepts for the acquisition of a complete description of the goals, requirements, and constraints related to a system design project. Within this environment, existing commercial specification and system design tools have been integrated into a CAE framework and new tools have been developed to support early requirement definition, specification flow control, early validation of specification, and specification data management.<>
{"title":"Towards a requirements definition, specification and system design environment","authors":"K. Müller-Glaser, J. Bortolazzi, Y. Tanurhan","doi":"10.1109/EURDAC.1992.246237","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246237","url":null,"abstract":"The authors provide an overview of techniques for the specification of complex, heterogeneous systems, i.e. microsystems or automotive control systems including hardware (analog and digital electronics, mechanical or optical actuators and sensors) and software. An approach to an integrated environment to support and control the requirement definition, specification and system design phases is described. This approach combines behavioral, functional, and data-oriented specifications based on formal languages, as well as knowledge-based concepts for the acquisition of a complete description of the goals, requirements, and constraints related to a system design project. Within this environment, existing commercial specification and system design tools have been integrated into a CAE framework and new tools have been developed to support early requirement definition, specification flow control, early validation of specification, and specification data management.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116859009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246200
H. Tamamoto, H. Yokoyama, Y. Narita
Assuming a stuck-at type fault, the authors discuss current testing for CMOS logic circuits where the random patterns generated by a linear feedback shift register (LFSR) are applied, and a dynamic power supply current is monitored. The LFSR is modified such that there exists a feedback from the outputs of a circuit under test to the LSFR. This modification is intended for amplifying the effect of a fault near a primary output on the dynamic current. In order to distinguish the dynamic current of a faulty circuit from the one of a fault-free circuit, two methods are discussed. One is the method where the waveform of the dynamic current is recognized using a neural network, and the other is the method where the mean dynamic current is calculated. Simulation results show that a high fault coverage can be obtained using a small number of test vectors.<>
{"title":"Random current testing for CMOS logic circuits by monitoring a dynamic power supply current","authors":"H. Tamamoto, H. Yokoyama, Y. Narita","doi":"10.1109/EURDAC.1992.246200","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246200","url":null,"abstract":"Assuming a stuck-at type fault, the authors discuss current testing for CMOS logic circuits where the random patterns generated by a linear feedback shift register (LFSR) are applied, and a dynamic power supply current is monitored. The LFSR is modified such that there exists a feedback from the outputs of a circuit under test to the LSFR. This modification is intended for amplifying the effect of a fault near a primary output on the dynamic current. In order to distinguish the dynamic current of a faulty circuit from the one of a fault-free circuit, two methods are discussed. One is the method where the waveform of the dynamic current is recognized using a neural network, and the other is the method where the mean dynamic current is calculated. Simulation results show that a high fault coverage can be obtained using a small number of test vectors.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127026810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246326
E. Pajarre, T. Ritoniemi, T. Tenhunen
The authors describe a circuit simulation, analysis and optimization software which can utilize the most common parallel processing hardware, i.e. the workstation network. The parallel processing ability has been implemented using an easy-to-use but powerful methodology. The efficiency of this methodology is demonstrated in terms of both CPU and programmer time. The feasibility of converting even large existing software systems for at least partial parallel execution is demonstrated. With a suitable set of tools the amount of changes which are needed is small. Despite the limited bandwidth of an Ethernet network, a set of networked computers can be used as an efficient parallel processor for some of the problems in electronic design automation.<>
{"title":"PAR-APLAC: parallel circuit analysis and optimization","authors":"E. Pajarre, T. Ritoniemi, T. Tenhunen","doi":"10.1109/EURDAC.1992.246326","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246326","url":null,"abstract":"The authors describe a circuit simulation, analysis and optimization software which can utilize the most common parallel processing hardware, i.e. the workstation network. The parallel processing ability has been implemented using an easy-to-use but powerful methodology. The efficiency of this methodology is demonstrated in terms of both CPU and programmer time. The feasibility of converting even large existing software systems for at least partial parallel execution is demonstrated. With a suitable set of tools the amount of changes which are needed is small. Despite the limited bandwidth of an Ethernet network, a set of networked computers can be used as an efficient parallel processor for some of the problems in electronic design automation.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"146 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129072651","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246186
Paul L. Harper, K. Scott
The VHSIC hardware description language (VHDL) Synthesis Special Interest Group (SSIG) has been working on the development of a standard VHDL package for synthesis. The efforts of the group have been divided into four different areas: logic type, representation of numeric types, specification of constraints, and special identifications. Each of these areas addresses an important part of the information required for synthesis of a VHDL model. An important decision of the group was to adopt the std logic type defined in the IEEE std logic 1164 package. The numeric types area was created in order to provide arithmetic capabilities based on the std logic value. The constraints area addresses design information beyond the functionality of the design that is still part of the specification. The special identifications area is a catch-all area for additional information about a design that may be useful to different aspects of the synthesis process.<>
{"title":"Towards a standard VHDL synthesis package","authors":"Paul L. Harper, K. Scott","doi":"10.1109/EURDAC.1992.246186","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246186","url":null,"abstract":"The VHSIC hardware description language (VHDL) Synthesis Special Interest Group (SSIG) has been working on the development of a standard VHDL package for synthesis. The efforts of the group have been divided into four different areas: logic type, representation of numeric types, specification of constraints, and special identifications. Each of these areas addresses an important part of the information required for synthesis of a VHDL model. An important decision of the group was to adopt the std logic type defined in the IEEE std logic 1164 package. The numeric types area was created in order to provide arithmetic capabilities based on the std logic value. The constraints area addresses design information beyond the functionality of the design that is still part of the specification. The special identifications area is a catch-all area for additional information about a design that may be useful to different aspects of the synthesis process.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114316338","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246214
Donald A. Lobo, B. Pangrle
A new approach to pipelined scheduling is demonstrated. Using a greedy algorithm to generate the initial solution and then applying a series of transformations to the graph is shown to be effective in obtaining optimal and near optimal results without resorting to an exhaustive search. The algorithm handles multicycle pipelined functional units leading to the generation of compact schedules. Using pipelined functional units, the effective throughput is increased and shorter latency times are produced. Thus, in the case of the optimized finite impulse response (FIR) filter, a throughput of three clock cycles, with a latency of nine clock cycles can be obtained using a functional unit specification of five one-cycle adders and three two-cycle pipelined multipliers. In this case the throughput is doubled, and the latency is improved by 33% using pipelined units over non-pipelined units.<>
{"title":"Generating pipelined datapaths using reduction techniques to shorten critical paths","authors":"Donald A. Lobo, B. Pangrle","doi":"10.1109/EURDAC.1992.246214","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246214","url":null,"abstract":"A new approach to pipelined scheduling is demonstrated. Using a greedy algorithm to generate the initial solution and then applying a series of transformations to the graph is shown to be effective in obtaining optimal and near optimal results without resorting to an exhaustive search. The algorithm handles multicycle pipelined functional units leading to the generation of compact schedules. Using pipelined functional units, the effective throughput is increased and shorter latency times are produced. Thus, in the case of the optimized finite impulse response (FIR) filter, a throughput of three clock cycles, with a latency of nine clock cycles can be obtained using a functional unit specification of five one-cycle adders and three two-cycle pipelined multipliers. In this case the throughput is doubled, and the latency is improved by 33% using pipelined units over non-pipelined units.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114321126","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246206
N. Ishiura, S. Yajima
The authors present a new fast fault simulation algorithm using a content addressable memory, which deals with zero-delay fault simulation of gate-level synchronous sequential circuits. The new algorithm attempts to reduce the computation time by processing many faults at a time on the assumption that a content addressable memory can be regarded as a single instruction multiple data (SIMD) type parallel computation machine. According to theoretical estimation, the speed performance of a simulator based on the proposed algorithm is comparable to that of a fast fault simulator implemented on a vector supercomputer for a circuit of about 2400 gates.<>
{"title":"Linear time fault simulation algorithm using a content addressable memory","authors":"N. Ishiura, S. Yajima","doi":"10.1109/EURDAC.1992.246206","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246206","url":null,"abstract":"The authors present a new fast fault simulation algorithm using a content addressable memory, which deals with zero-delay fault simulation of gate-level synchronous sequential circuits. The new algorithm attempts to reduce the computation time by processing many faults at a time on the assumption that a content addressable memory can be regarded as a single instruction multiple data (SIMD) type parallel computation machine. According to theoretical estimation, the speed performance of a simulator based on the proposed algorithm is comparable to that of a fast fault simulator implemented on a vector supercomputer for a circuit of about 2400 gates.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126468522","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246342
Stephen E. Lim, D. C. Hendry, P. Yeung
Synthesis systems that take VHSIC hardware description language (VHDL) as input are now widespread, and impose certain constraints, or conditions of usage, on the designer, most of which help to achieve a fast turnaround. The authors report experiences with using VHDL-based synthesis in a design environment where delivering workable circuits in short schedules is of paramount importance. Results show that a fully automated hardware description language (HDL)-based solution is not possible with present synthesis technology; designer intervention is almost always required.<>
{"title":"Experiences and issues in VHDL-based synthesis","authors":"Stephen E. Lim, D. C. Hendry, P. Yeung","doi":"10.1109/EURDAC.1992.246342","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246342","url":null,"abstract":"Synthesis systems that take VHSIC hardware description language (VHDL) as input are now widespread, and impose certain constraints, or conditions of usage, on the designer, most of which help to achieve a fast turnaround. The authors report experiences with using VHDL-based synthesis in a design environment where delivering workable circuits in short schedules is of paramount importance. Results show that a fully automated hardware description language (HDL)-based solution is not possible with present synthesis technology; designer intervention is almost always required.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133634151","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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