A Framework for Automatic Assembly Program Generator (A^2PG) for Verification and Testing of Processor Cores

Abstract

Pre-silicon functional design verification, performance measurements and post-silicon functional testing of processor cores consume the major portion of time and cost investment in any concept-to-silicon design flow. Most of the tools reported in the literature are based on function/faultindependent test generation schemes which cannot be effectively employed for verification or testing of specific functional behavior or for generating inputs for performance measurement of a specific parameter or functional unit in the design. In addition, the crucial bottleneck with existing tools is their scalability with larger designs. It is wellstudied and reported in the literature that for a tool to be scalable with larger designs, it is important to handle the design at higher levels of abstraction, typically, at the RTL level. In this paper, we present an Automatic Assembly Program Generator (A^2 PG), that handles the design at the behavioral RTL level and is based on function-oriented test generation schemes, hence making it scalable and usable for some specific tasks as mentioned above.