S. Mukhopadhyay, A. Raychowdhury, H. Mahmoodi, K. Roy
In this paper, we develop a method to analyze the probability of access failure in SRAM array (due to random Vt variation in transistors) by jointly considering variations in cell and senseamplifiers. Our analysis shows that, improving robustness of senseamplifier is extremely important for reducing memory access failure probability and improving yield. We present a process variation tolerant sense amplifier suitable for SRAM array designed in sub- 100nm CMOS technologies. The proposed technique reduces the failure probability of sense amplifiers by more than 80% with negligible penalty in the sensing delay.
{"title":"Leakage Current Based Stabilization Scheme for Robust Sense-Amplifier Design for Yield Enhancement in Nano-scale SRAM","authors":"S. Mukhopadhyay, A. Raychowdhury, H. Mahmoodi, K. Roy","doi":"10.1109/ATS.2005.73","DOIUrl":"https://doi.org/10.1109/ATS.2005.73","url":null,"abstract":"In this paper, we develop a method to analyze the probability of access failure in SRAM array (due to random Vt variation in transistors) by jointly considering variations in cell and senseamplifiers. Our analysis shows that, improving robustness of senseamplifier is extremely important for reducing memory access failure probability and improving yield. We present a process variation tolerant sense amplifier suitable for SRAM array designed in sub- 100nm CMOS technologies. The proposed technique reduces the failure probability of sense amplifiers by more than 80% with negligible penalty in the sensing delay.","PeriodicalId":373563,"journal":{"name":"14th Asian Test Symposium (ATS'05)","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123219812","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
VLSI circuits have been traditionally tested individually following manufacture; the same tests being applied to all ICs. However, as manufacturing test costs continue to show a disproportionate increase in relation to IC fabrication costs, innovative new statistical methods are being introduced to optimize testing. Such methods fall into two broad categories: those that exploit statistical information in regard to the variation of process parameters on wafers, and those that exploit the statistics of defect distributions on wafers. This tutorial presents test methodologies that span both these categories and illustrate their effectiveness with experimental results from a number of recent studies on production circuits from LSI Logic, IBM, Intel and TI
{"title":"T2: Statistical Methods for VLSI Test and Burn-in Optimization","authors":"A. Singh","doi":"10.1109/ATS.2005.104","DOIUrl":"https://doi.org/10.1109/ATS.2005.104","url":null,"abstract":"VLSI circuits have been traditionally tested individually following manufacture; the same tests being applied to all ICs. However, as manufacturing test costs continue to show a disproportionate increase in relation to IC fabrication costs, innovative new statistical methods are being introduced to optimize testing. Such methods fall into two broad categories: those that exploit statistical information in regard to the variation of process parameters on wafers, and those that exploit the statistics of defect distributions on wafers. This tutorial presents test methodologies that span both these categories and illustrate their effectiveness with experimental results from a number of recent studies on production circuits from LSI Logic, IBM, Intel and TI","PeriodicalId":373563,"journal":{"name":"14th Asian Test Symposium (ATS'05)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116617595","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
As electronic systems are becoming more complex with higher performance and require higher reliability, system test is becoming a very challenging task. Traditionally, functional test has been used to detect various design and manufacturing defects for electronic systems. However, functional test doesn’t work efficiently for large and complex systems specially when debugging and diagnosis of failure conditions is targeted. Boundary scan based test technology is being used for testing circuit boards in the industry for over a decade after being standardized by IEEE. This technology provides an access path to all the pins on all boundary scan-able chips on a circuit board.
{"title":"Efficient Test Architecture based on Boundary Scan for Comprehensive System Test","authors":"T. Chakraborty","doi":"10.1109/ATS.2005.54","DOIUrl":"https://doi.org/10.1109/ATS.2005.54","url":null,"abstract":"As electronic systems are becoming more complex with higher performance and require higher reliability, system test is becoming a very challenging task. Traditionally, functional test has been used to detect various design and manufacturing defects for electronic systems. However, functional test doesn’t work efficiently for large and complex systems specially when debugging and diagnosis of failure conditions is targeted. Boundary scan based test technology is being used for testing circuit boards in the industry for over a decade after being standardized by IEEE. This technology provides an access path to all the pins on all boundary scan-able chips on a circuit board.","PeriodicalId":373563,"journal":{"name":"14th Asian Test Symposium (ATS'05)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130631319","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Due to the increasing test data volume needed to test corebased System-on-Chip, several test scheduling techniques minimizing the test application time have been proposed. In contrast to approaches where a fixed test set for each core is assumed, we explore the possibility to use overlapping test patterns from the tests in the system. The overlapping tests serves as alternatives to the original dedicated test for the cores and, if selected, they are transported to the cores in a broadcasted manner so that several cores are tested concurrently. We have made use of a Constraint Logic Programming technique to select suitable tests for each core in the system and schedule the selected tests such that the test application time is minimized while designer-specified hardware constraints are satisfied. The experimental results indicate that we can on average reduce the test application time with 23%.
{"title":"SOC Test Scheduling with Test Set Sharing and Broadcasting","authors":"Anders Larsson, E. Larsson, P. Eles, Zebo Peng","doi":"10.1109/ATS.2005.100","DOIUrl":"https://doi.org/10.1109/ATS.2005.100","url":null,"abstract":"Due to the increasing test data volume needed to test corebased System-on-Chip, several test scheduling techniques minimizing the test application time have been proposed. In contrast to approaches where a fixed test set for each core is assumed, we explore the possibility to use overlapping test patterns from the tests in the system. The overlapping tests serves as alternatives to the original dedicated test for the cores and, if selected, they are transported to the cores in a broadcasted manner so that several cores are tested concurrently. We have made use of a Constraint Logic Programming technique to select suitable tests for each core in the system and schedule the selected tests such that the test application time is minimized while designer-specified hardware constraints are satisfied. The experimental results indicate that we can on average reduce the test application time with 23%.","PeriodicalId":373563,"journal":{"name":"14th Asian Test Symposium (ATS'05)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125596162","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a new low power BIST TPG scheme. It uses a transition monitoring window (TMW) that is comprised of a transition monitoring window block and a MUX. When random test patterns are generated by an LFSR, transitions of those patterns satisfy pseudo-random Gaussian distribution. The proposed technique represses transitions of patterns using the k-value which is a standard that is obtained from the distribution of TMW to observe over transitive patterns causing high power dissipation in a scan chain. Experimental results show that the proposed BIST TPG schemes can reduce scan transition by about 60% without performance loss in ISCAS’89 benchmark circuits that have large number scan inputs.
{"title":"A New Low Power Test Pattern Generator using a Transition Monitoring Window based on BIST Architecture","authors":"Youbean Kim, M. Yang, Yong Lee, Sungho Kang","doi":"10.1109/ATS.2005.12","DOIUrl":"https://doi.org/10.1109/ATS.2005.12","url":null,"abstract":"This paper presents a new low power BIST TPG scheme. It uses a transition monitoring window (TMW) that is comprised of a transition monitoring window block and a MUX. When random test patterns are generated by an LFSR, transitions of those patterns satisfy pseudo-random Gaussian distribution. The proposed technique represses transitions of patterns using the k-value which is a standard that is obtained from the distribution of TMW to observe over transitive patterns causing high power dissipation in a scan chain. Experimental results show that the proposed BIST TPG schemes can reduce scan transition by about 60% without performance loss in ISCAS’89 benchmark circuits that have large number scan inputs.","PeriodicalId":373563,"journal":{"name":"14th Asian Test Symposium (ATS'05)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122225261","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Jahangiri, N. Mukherjee, Wu-Tung Cheng, S. Mahadevan, R. Press
Reduced pin count testing (RPCT) has proven to be an effective solution to reduce structural test costs in a manufacturing environment. Traditionally, RPCT has focused on stuck-at faults and IO loop-back tests. However, as circuit feature sizes shrink and new technology nodes employed, at-speed tests are becoming critical to assure low defect levels. In this paper, we extend the RPCT technique to allow application of atspeed test patterns using low cost testers that are seriously pin limited. Existing boundary scan cells are modified to facilitate the application of at-speed patterns thereby having minimal impact on the design and test area overhead.
{"title":"Achieving High Test Quality with Reduced Pin Count Testing","authors":"J. Jahangiri, N. Mukherjee, Wu-Tung Cheng, S. Mahadevan, R. Press","doi":"10.1109/ATS.2005.19","DOIUrl":"https://doi.org/10.1109/ATS.2005.19","url":null,"abstract":"Reduced pin count testing (RPCT) has proven to be an effective solution to reduce structural test costs in a manufacturing environment. Traditionally, RPCT has focused on stuck-at faults and IO loop-back tests. However, as circuit feature sizes shrink and new technology nodes employed, at-speed tests are becoming critical to assure low defect levels. In this paper, we extend the RPCT technique to allow application of atspeed test patterns using low cost testers that are seriously pin limited. Existing boundary scan cells are modified to facilitate the application of at-speed patterns thereby having minimal impact on the design and test area overhead.","PeriodicalId":373563,"journal":{"name":"14th Asian Test Symposium (ATS'05)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131230500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this talk, the EDT technology was introduced briefly along with a description of the hardware and the methodology used to achieve high test-data compression. The advantages of the approach in terms of encoding capacity, ability to handle unknowns, minimal hardware overhead, and close resemblance to a conventional ATPG flow were discussed. Since the technology requires very few pins to drive the decompressor from an ATE and observe responses at the output, it is attractive for burn-in test, core test, multisite testing, and is suitable for parts tested on VLCTs. The presentation touched upon these test techniques that directly benefit from using the proposed solution. With newer technology nodes, diagnosis is becoming critical for yield ramp up, faster time to volume, and first silicon debug. No compression solution is complete without an easy way to diagnose failures during manufacturing test. The ability to perform direct diagnosis from compressed patterns within the EDT framework were presented
{"title":"Improving Test Quality Using Test Data Compression","authors":"N. Mukherjee","doi":"10.1109/ATS.2005.70","DOIUrl":"https://doi.org/10.1109/ATS.2005.70","url":null,"abstract":"In this talk, the EDT technology was introduced briefly along with a description of the hardware and the methodology used to achieve high test-data compression. The advantages of the approach in terms of encoding capacity, ability to handle unknowns, minimal hardware overhead, and close resemblance to a conventional ATPG flow were discussed. Since the technology requires very few pins to drive the decompressor from an ATE and observe responses at the output, it is attractive for burn-in test, core test, multisite testing, and is suitable for parts tested on VLCTs. The presentation touched upon these test techniques that directly benefit from using the proposed solution. With newer technology nodes, diagnosis is becoming critical for yield ramp up, faster time to volume, and first silicon debug. No compression solution is complete without an easy way to diagnose failures during manufacturing test. The ability to perform direct diagnosis from compressed patterns within the EDT framework were presented","PeriodicalId":373563,"journal":{"name":"14th Asian Test Symposium (ATS'05)","volume":"109 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133518781","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In the present day, most of the designs for testability (DFT) strategies are based on full and partial scan designs. Different methods are used to select the flip-flops for the scan path, which are based on the structure of the circuit, and some testability measures. However, most of the methods just focus on a single method and at most two for partial scan path design. In this paper, we propose a new approach for selection of flip-flops in partial scan path design. We try to incorporate three different methods into one and optimize them using genetic algorithm. The testability approach is used to estimate how the selection of a particular flip-flop affects its neighboring flip-flops. Focus is also given to those flip-flops whose selection tends to break maximum number of cycles. Finally we try to optimize is to minimize the overall power consumption of the modified circuit. The experimental results show that though it is not always possible to improve upon the performances of techniques which focus only on single objective, on an average fairly good results are obtained in terms of fault coverage, number of vectors and the power consumption.
{"title":"A Unified Approach to Partial Scan Design using Genetic Algorithm","authors":"Varun Arora, I. Sengupta","doi":"10.1109/ATS.2005.18","DOIUrl":"https://doi.org/10.1109/ATS.2005.18","url":null,"abstract":"In the present day, most of the designs for testability (DFT) strategies are based on full and partial scan designs. Different methods are used to select the flip-flops for the scan path, which are based on the structure of the circuit, and some testability measures. However, most of the methods just focus on a single method and at most two for partial scan path design. In this paper, we propose a new approach for selection of flip-flops in partial scan path design. We try to incorporate three different methods into one and optimize them using genetic algorithm. The testability approach is used to estimate how the selection of a particular flip-flop affects its neighboring flip-flops. Focus is also given to those flip-flops whose selection tends to break maximum number of cycles. Finally we try to optimize is to minimize the overall power consumption of the modified circuit. The experimental results show that though it is not always possible to improve upon the performances of techniques which focus only on single objective, on an average fairly good results are obtained in terms of fault coverage, number of vectors and the power consumption.","PeriodicalId":373563,"journal":{"name":"14th Asian Test Symposium (ATS'05)","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133536884","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Quantum computing is a recently developed approach to information processing, which is based on quantum mechanics rather than classical physics. Information is represented by quantum bits (qubits) that correspond to microscopic states such as photon polarization. Up to 2n n-bit words can be stored simultaneously in n qubits, implying a type of massive parallelism. Powerful forms of quantum interaction such as interference and entanglement exist which have no counterparts in classical computer science. Some important and hitherto intractable problems such as prime factorization of large numbers can be solved efficiently using quantum methods. In practice, however, quantum computing devices and circuits are extremely difficult to design and build, since they are nanoscale in size and operate at very low energy levels. Consequently, they have many more failure modes than classical (non-quantum) circuits. For example, quantum signal states are inherently unstable and tend to decay rapidly due to interaction with the environment (decoherence). Quantum gate operations are defined by continuous parameters that allow small errors to arise and propagate to other gates. Furthermore, state measurement is probabilistic and the measurement process itself affects the state being measured. This talk will review the history and development of quantum circuits, with emphasis on their failure modes and testing requirements. It will be seen that quantum circuits are highly testable for classical faults. However, they are also subject to various complex, nonclassical failure modes, which are still not well understood. Some methods for error correction and recovery that have been developed specifically for quantum circuits will also be reviewed.
{"title":"Faults and Tests in Quantum Circuits","authors":"J. Hayes","doi":"10.1109/ATS.2005.59","DOIUrl":"https://doi.org/10.1109/ATS.2005.59","url":null,"abstract":"Quantum computing is a recently developed approach to information processing, which is based on quantum mechanics rather than classical physics. Information is represented by quantum bits (qubits) that correspond to microscopic states such as photon polarization. Up to 2n n-bit words can be stored simultaneously in n qubits, implying a type of massive parallelism. Powerful forms of quantum interaction such as interference and entanglement exist which have no counterparts in classical computer science. Some important and hitherto intractable problems such as prime factorization of large numbers can be solved efficiently using quantum methods. In practice, however, quantum computing devices and circuits are extremely difficult to design and build, since they are nanoscale in size and operate at very low energy levels. Consequently, they have many more failure modes than classical (non-quantum) circuits. For example, quantum signal states are inherently unstable and tend to decay rapidly due to interaction with the environment (decoherence). Quantum gate operations are defined by continuous parameters that allow small errors to arise and propagate to other gates. Furthermore, state measurement is probabilistic and the measurement process itself affects the state being measured. This talk will review the history and development of quantum circuits, with emphasis on their failure modes and testing requirements. It will be seen that quantum circuits are highly testable for classical faults. However, they are also subject to various complex, nonclassical failure modes, which are still not well understood. Some methods for error correction and recovery that have been developed specifically for quantum circuits will also be reviewed.","PeriodicalId":373563,"journal":{"name":"14th Asian Test Symposium (ATS'05)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115417865","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Bhaskar, M. Prasanth, V. Kamakoti, Kailasnath Maneparambil
Pre-silicon functional design verification, performance measurements and post-silicon functional testing of processor cores consume the major portion of time and cost investment in any concept-to-silicon design flow. Most of the tools reported in the literature are based on function/faultindependent test generation schemes which cannot be effectively employed for verification or testing of specific functional behavior or for generating inputs for performance measurement of a specific parameter or functional unit in the design. In addition, the crucial bottleneck with existing tools is their scalability with larger designs. It is wellstudied and reported in the literature that for a tool to be scalable with larger designs, it is important to handle the design at higher levels of abstraction, typically, at the RTL level. In this paper, we present an Automatic Assembly Program Generator (A^2 PG), that handles the design at the behavioral RTL level and is based on function-oriented test generation schemes, hence making it scalable and usable for some specific tasks as mentioned above.
{"title":"A Framework for Automatic Assembly Program Generator (A^2PG) for Verification and Testing of Processor Cores","authors":"K. Bhaskar, M. Prasanth, V. Kamakoti, Kailasnath Maneparambil","doi":"10.1109/ATS.2005.10","DOIUrl":"https://doi.org/10.1109/ATS.2005.10","url":null,"abstract":"Pre-silicon functional design verification, performance measurements and post-silicon functional testing of processor cores consume the major portion of time and cost investment in any concept-to-silicon design flow. Most of the tools reported in the literature are based on function/faultindependent test generation schemes which cannot be effectively employed for verification or testing of specific functional behavior or for generating inputs for performance measurement of a specific parameter or functional unit in the design. In addition, the crucial bottleneck with existing tools is their scalability with larger designs. It is wellstudied and reported in the literature that for a tool to be scalable with larger designs, it is important to handle the design at higher levels of abstraction, typically, at the RTL level. In this paper, we present an Automatic Assembly Program Generator (A^2 PG), that handles the design at the behavioral RTL level and is based on function-oriented test generation schemes, hence making it scalable and usable for some specific tasks as mentioned above.","PeriodicalId":373563,"journal":{"name":"14th Asian Test Symposium (ATS'05)","volume":"125 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114907365","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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