Uniform Support for Information Handling and Problem Solving Required by the VLSI Design Process

Abstract

This paper addresses software engineering issues in designing software environments for managing the voluminous and non-homogeneous information generated during the VLSI design process. This involves not only a uniform logical framework within which to represent this information but also to provide a means to explicitly record the procedures used in creating and collecting this information. Our approach is to organize this information under a hierarchical framework based on grammars. The advantage of this approach lies in the ability to integrate both methodology information and CAD tools within this uniform framework. The approach is used to address problems which cannot be solved by designing sophisticated but isolated tools.